Semiconductor Chip Connection Lines With Resistance Sections
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Solution Overview
Problem
Conventional power transistors face issues with high on-resistance, high output capacitance, and inhomogeneous switching behavior due to the use of vertical field plates, leading to over-voltage peaks and inefficient chip space utilization.
Innovation Solution
A semiconductor chip design with a semiconductor body featuring an active and non-active transistor region, where connection lines with resistance sections are used to connect transistor cells to contact terminal pads, with resistance sections having a locally reduced cross-sectional area or increased specific resistance, allowing for improved switching behavior and reduced output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical field plates are used to achieve low on-resistance, then on-resistance is reduced, but output capacitance increases
Solution Approach 1:
The patent applies local quality by creating resistance sections with locally reduced cross-sectional area or locally increased specific resistance in specific regions of the connection lines. This allows different parts of the connection structure to have different electrical properties - the resistance sections provide damping where needed while other regions maintain low resistance for current conduction, thereby reducing output capacitance effects without sacrificing overall on-resistance performance
Solution Approach 2:
The patent changes physical parameters of the connection lines by modifying either the cross-sectional area or specific resistance in localized regions. This parameter change creates resistance sections that provide the necessary damping effect to reduce output capacitance and over-voltage peaks, while the overall low on-resistance is maintained through proper design of the resistance section characteristics
2Object-affected harmful factors
If damping resistor is connected in series with field plates to reduce over-voltage peaks, then over-voltage peaks are reduced, but chip space is wasted
Solution Approach 1:
The patent merges the damping function with the existing connection lines by creating resistance sections within them, rather than adding separate damping resistors. The connection lines serve dual purposes: electrical connection and damping function. This integration eliminates the need for additional discrete components and reduces chip space consumption while still achieving over-voltage peak reduction
Solution Approach 2:
The connection lines are designed to perform multiple functions: they provide electrical connection between transistor cells and contact terminal pads, and simultaneously serve as damping elements through their resistance sections. This multi-functionality reduces the total component count and optimizes chip space usage while addressing the over-voltage peak problem
3Ease of manufacture
If conventional transistor design is used, then manufacturing is simplified, but switching behavior is inhomogeneous
Solution Approach 1:
The patent applies local quality by introducing resistance sections at specific locations in the connection lines, particularly in regions where damping is most effective. This localized modification achieves homogeneous switching behavior across all transistor cells without requiring complex manufacturing changes, as the resistance sections can be formed using standard semiconductor fabrication techniques
Solution Approach 2:
The patent segments the connection lines into different functional regions: low-resistance sections for current conduction and resistance sections with locally reduced cross-sectional area or increased specific resistance for damping. This segmentation allows each part to perform its specific function optimally, ensuring homogeneous switching behavior while maintaining manufacturing simplicity through modular design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low on-resistance, low output capacitance, and homogeneous switching behavior, reducing over-voltage peaks and optimizing chip space usage.
Implementation Method 1
Each of the connection lines comprises a resistance section wherein each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region
Data Source
AI summary
A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.