Semiconductor Chip Rings for Uniform Copper Plating

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Solution Overview

Problem

The miniaturization of wiring in semiconductor devices leads to increased resistance in seed-Cu layers, resulting in non-uniform copper plating thickness due to voltage drops in the wafer middle portion, and existing solutions either generate dust or require remodeling of the plating device.

Innovation Solution

The introduction of electrically connected chip rings surrounding the chip regions acts as a low-resistance current supply path, ensuring uniform current distribution and plating thickness across the wafer surface without remodeling the plating solution or device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If current is supplied from wafer peripheral terminals, then plating process is simple, but voltage drop occurs in wafer middle portion causing non-uniform plating thickness

Engineering Contradiction:
Improveplating process complexityVSAvoidcopper plating thickness uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The chip rings serve as intermediary current supply paths between the peripheral terminals and the seed-Cu layer in the wafer middle portion. These rings conduct current directly to the seed-Cu layer, acting as mediators that eliminate voltage drops and ensure uniform current distribution without requiring terminal relocation or device remodeling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If a current supply source is added in the wafer middle portion to suppress voltage drop, then plating uniformity improves, but dust is generated on the wafer

Engineering Contradiction:
Improveplating thickness uniformityVSAvoiddust generation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The chip rings, which are standard structures in semiconductor manufacturing, are given a dual function: they serve both as structural elements for chip separation and as current supply paths for the plating process. This multi-functionality allows uniform plating without adding separate current supply sources that would generate dust.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If plating solution resistance distribution is controlled to suppress voltage drop, then plating uniformity improves, but plating device remodeling is required

Engineering Contradiction:
Improveplating thickness uniformityVSAvoidplating device structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention makes the chip rings self-serve as current supply paths, utilizing the existing wafer structure to provide the necessary current distribution. This self-service approach eliminates the need for external device modifications or complex plating solution formulations, maintaining manufacturing simplicity while achieving uniform plating.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces voltage drops and achieves uniform copper plating thickness regardless of seed layer thickness, improving process capability and avoiding dust generation or device remodeling.

Implementation Method 1

the plurality of chip rings are electrically connected to one another

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

an electrolytic plating process which is advantageous in forming fine patterns has been usually used

Methodology Applied
Scientific EffectElectrolytic plating: Electroplating

Data Source

PatentUS7652351B2Semiconductor device and method of manufacturing the same
Publication Date: 2010.01.26 KIOXIA CORP
  • US7652351B2 patent drawing
  • US7652351B2 patent drawing
  • US7652351B2 patent drawing

AI summary

A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.