Semiconductor Chip Seal Ring Design for Contamination Protection
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Solution Overview
Problem
Integration of sensor devices with processing circuitry on semiconductor chips is prone to damage during the dicing process and contamination, which affects the reliability of the chips, especially for CMOS technology sensitive to contaminants like humidity and ions.
Innovation Solution
A semiconductor chip design featuring a stack with insulating and metal layers, including a first seal ring to protect from lateral impacts and a second seal ring to prevent contaminant infiltration, both implemented between the substrate and passivation layer, with a contact layer for electrical connection outside the sealed area to bypass the seal ring, effectively shielding contaminants and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If sensor devices and processing circuitry are integrated on the same semiconductor substrate, then the size of the sensor device is significantly reduced and manufacturing efficiency is improved, but the chip becomes vulnerable to damage during dicing and contamination from the sensor area
Solution Approach 1:
The chip is divided into distinct sensor area and processing area with a seal ring structure that physically segments the two regions. This segmentation allows the sensor device to be miniaturized while protecting the processing circuitry from contaminants originating in the sensor area.
Solution Approach 2:
A seal ring structure is introduced as an intermediary element between the sensor area and processing area. This seal ring acts as a barrier that prevents contaminant infiltration while allowing the integrated design to maintain its compact size.
2Strength
If a seal ring is provided at the edge of the chip to protect from damage, then the protection against lateral impact is improved, but the chip remains vulnerable to contaminant infiltration from the sensor area to the processing area
Solution Approach 1:
The protective structure is segmented into two distinct seal ring components: a first seal ring at the chip edge for mechanical protection, and a second seal ring between the sensor and processing areas for contamination protection. This segmentation addresses both protection needs simultaneously.
Solution Approach 2:
Different regions of the chip receive different types of protection tailored to their specific needs. The first seal ring provides mechanical strength at the edge, while the second seal ring provides contamination barriers in the critical interface region between sensor and processing areas.
3Adaptability or versatility
If the sensor area is left open for sensor operation, then the sensor function is maintained, but contaminants can infiltrate from the sensor area to the processing area
Solution Approach 1:
The second seal ring acts as an intermediary barrier that allows the sensor area to remain open and functional while preventing contaminant migration to the processing area. The seal ring is positioned to block contaminant paths without interfering with sensor operation.
Solution Approach 2:
The seal ring structure is locally positioned at the boundary between sensor and processing areas, providing contamination protection only where needed. This localized approach maintains sensor operation capability while blocking contaminant infiltration paths to the sensitive processing circuitry.
Data Source
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AI summary
Aspects of the invention relate to a semiconductor chip comprising a substrate (1) and a stack (4) arranged on the substrate (1). The stack (4) comprises one or more insulating layers (2) and one or more metal layers (3). The chip comprises a sensor device (5) arranged in a sensor area (SA) of the semiconductor chip and processing circuitry (6) arranged in a processing area (PA) of the semiconductor chip. The chip further comprises connection circuitry (7) configured to provide an electrical connection between the sensor device (5) and the processing circuitry (6). A first seal ring structure (10) is arranged between an outer edge (ED) of the chip and an inner area (IA) of the chip. The inner area (IA) of the chip encompasses the sensor area (SA) and the processing area (PA). A second seal ring structure (11) is arranged between the sensor area (SA) and the processing area (PA) and configured to constrain an infiltration of contaminants from the sensor area (SA) to the processing area (PA).