Semiconductor Chip Stack Layout for Shorter Wire Bonds
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Solution Overview
Problem
The stacking of semiconductor chips in semiconductor devices can lead to difficulties in wire bonding due to the arrangement of metal pads and the orientation of the chips, resulting in longer bonding wires, increased resistance, and higher chances of chip cracking.
Innovation Solution
A spiral stacking arrangement of semiconductor chips with metal pads positioned to overlap with the underlying chips, reducing the length of bonding wires and minimizing the angle of wire bonding, thereby enhancing the stability and reducing the likelihood of chip cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are stacked in a conventional arrangement, then the device can be manufactured, but the bonding wire length increases and resistance increases
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked arrangement where chips are positioned at different heights (Z-axis) while maintaining overlapping projections on the substrate. This dimensional change allows bonding wires to connect between vertically separated pads, reducing the lateral wire length and associated resistance while improving connection stability.
2Reliability
If semiconductor chips are stacked in a conventional arrangement, then the device can be manufactured, but the angle of wire bonding increases and chip cracking likelihood increases
Solution Approach 1:
By stacking chips at different heights and positioning pads to overlap in planar projection, the patent creates a vertical separation between connection points. This allows bonding wires to follow a more direct vertical path rather than long lateral paths, reducing the bonding angle and minimizing mechanical stress on chips during the wire bonding process, thereby reducing cracking risk.
Solution Approach 2:
The patent positions specific pads on different chips to overlap in the planar direction while maintaining vertical separation. This local optimization of pad positioning creates favorable bonding conditions at specific locations without requiring a complete redesign of the entire chip stack, enabling easier wire bonding at critical connection points.
3Area of stationary object
If metal pads are positioned away from the center, then chip area can be optimized, but bonding wire length increases and resistance increases
Solution Approach 1:
The patent allows pads to be positioned at optimized locations on each chip (not necessarily at the center) while using vertical stacking to create overlapping projections. This enables pad placement that optimizes chip area utilization while the vertical dimension compensates for the lateral separation, maintaining short bonding wire lengths and low resistance through the height difference between stacked chips.
Data Source
AI summary
In one embodiment, a semiconductor device includes a substrate, one or more first substrate pads provided on the substrate, and one or more first chips provided on the substrate and located in a first direction from the first substrate pads, each of the first chips including one or more first chip pads electrically connected to the first substrate pads. The device further includes one or more second substrate pads provided on the substrate, and one or more second chips provided on the first chips and located in a second direction from the second substrate pads, the second direction intersecting the first direction, each of the second chips including one or more second chip pads electrically connected to the second substrate pads. Moreover, each of the second chip pads is located to overlap with a highest first chip of the first chips in planar view.