Semiconductor Chip Stack Interconnect with Asymmetric Thermal Columns
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Solution Overview
Problem
Current interconnect technologies for semiconductor chip stacks face challenges such as warpage, stress, and ion migration due to differences in material coefficients of expansion and high junction temperatures, especially when using gold or solder paste, which are inadequate for miniaturized and highly miniaturized chip connections.
Innovation Solution
A semiconductor chip stack is formed with a connection comprising a first column of high thermal activity material and a second column, where the first column is smaller in volume and has a higher thermal activity than the second column, allowing for low-temperature joining and minimizing thermal stress, and the aspect ratio of the connection is 0.5 or higher in the height direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold is used as junction material for direct bonding, then electrical connection between chips is achieved, but thermocompression at 350°C causes warpage, bending, and damage to semiconductor chips
Solution Approach 1:
The patent changes the material parameter of the junction from traditional gold to a copper-based alloy with specific composition (Cu: 60-80 at%, Zn: 10-30 at%, Ga: 0.1-5 at%). This material substitution enables bonding at lower temperatures (200-300°C) while maintaining electrical connection reliability, thus resolving the contradiction between connection reliability and joining temperature.
Solution Approach 2:
The patent uses a composite alloy material combining Cu, Zn, and Ga elements. The Cu-Zn base provides mechanical strength and electrical conductivity, while Ga addition enhances diffusion bonding capability at lower temperatures. This composite material approach achieves reliable electrical connection without requiring high-temperature thermocompression that causes chip warpage and damage.
2Temperature
If conventional solder paste is used for low-temperature bonding at 250°C, then joining temperature is reduced, but the paste state at joining time makes it difficult to secure desired space between chips
Solution Approach 1:
The patent changes the physical state parameter of the bonding material from paste (conventional) to a controlled deposition structure (invention). By depositing the Cu-Zn-Ga alloy as a structured junction with specific morphology and composition, the material maintains appropriate spacing between chips during low-temperature bonding, avoiding the flow and spreading issues of conventional solder paste.
3Ease of manufacture
If conventional paste with large particle diameter is used for mounting, then ease of manufacture is improved, but the particles are too large for interconnecting miniaturized electrodes
Solution Approach 1:
The patent changes the size parameter of the bonding material particles through controlled deposition of the Cu-Zn-Ga alloy. The deposition process creates a junction structure with dimensions suitable for miniaturized electrodes (sub-100 micrometer scale), while the material's inherent properties maintain ease of manufacture through standardized deposition techniques. This resolves the contradiction between particle size and manufacturability.
4Length of moving object
If narrow spacing between electrodes is used for miniaturization, then device size is reduced, but ion migration causes short circuits between electrodes
Solution Approach 1:
The patent changes the material composition parameter of the junction to Cu-Zn-Ga alloy, where the specific combination of elements creates a diffusion barrier effect. The Ga component particularly enhances resistance to ion migration by forming a stable intermetallic structure that blocks ion transport pathways. This allows narrow electrode spacing to be maintained without suffering from ion migration-induced short circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables strong, low-temperature joining of semiconductor chips with reduced thermal stress and inhibited ion migration, suitable for miniaturized chip connections with precise alignment and reduced risk of short circuits.
Implementation Method 1
the first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column
Data Source
AI summary
A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.