Semiconductor Chip Stack Package Using Same-Metal Interconnections
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Solution Overview
Problem
Current semiconductor chip technologies face challenges in reducing the size of surface mount devices while maintaining high physical strength and performance, especially in integrating multiple semiconductor chips into a single package for portable electronic products.
Innovation Solution
A semiconductor chip stack package design featuring a semiconductor substrate with a semiconductor device, dielectric, top metal, deep via, interconnection, and bump, where the bump, top metal, and deep via are formed of the same metal to facilitate efficient electrical connections and reduce resistance, enabling improved performance and bonding strength when stacked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated into one package, then the size of surface mount devices is reduced, but the physical strength and reliability of the package may deteriorate
Solution Approach 1:
The patent divides the package into multiple independent semiconductor chip layers, each maintaining its structural integrity. The chips are stacked vertically rather than placed horizontally, segmenting the package volume into discrete functional units that can be independently manufactured and tested, thus reducing overall package size while maintaining individual chip strength
Solution Approach 2:
The patent employs composite material structures including metal bumps, dielectric layers, and conductive interconnections to create a multi-material stack. This composite approach allows each material to contribute its optimal properties (mechanical strength, electrical conductivity, insulation) to the overall package structure, enabling size reduction without sacrificing physical strength
2Volume of moving object
If multiple semiconductor chips are integrated into one package, then the size of surface mount devices is reduced, but the performance and reliability of the semiconductor chips may deteriorate
Solution Approach 1:
The patent implements preliminary bonding of semiconductor chips to substrate and interconnection structures before final package assembly. This preliminary action allows for pre-testing and quality assurance of each chip layer, ensuring reliability is established early in the manufacturing process before the chips are stacked and enclosed in the final compact package
Solution Approach 2:
The patent utilizes parameter changes in the interconnection structures, including controlled resistance values, conductive material compositions, and geometric dimensions of bonding paths. By optimizing these parameters, the patent maintains low resistance electrical connections between stacked chips, preserving signal integrity and performance despite the reduced package size
3Reliability
If bump, top metal, and deep via are formed of the same metal, then electrical connection efficiency is improved, but manufacturing complexity may increase
Solution Approach 1:
The patent applies universality by using the same metal material for multiple functions: as bumps for inter-chip bonding, as top metal interconnections, and as deep via fill material. This multi-functional use of a single metal type simplifies the material inventory and processing steps compared to using different metals for each function, thereby reducing manufacturing complexity while maintaining excellent electrical connection efficiency
Solution Approach 2:
The patent employs homogeneity by forming bumps, top metal, and deep via from the same metal material, creating a uniform electrical connection path throughout the stack. This homogeneous material approach ensures consistent electrical properties (conductivity, resistance, bonding characteristics) across all connection points, improving reliability while simplifying manufacturing processes through standardized material handling
Data Source
AI summary
Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.