Semiconductor Chip Stack Sealing with Dual Elastic Modulus Materials
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Solution Overview
Problem
Conventional semiconductor devices using CoC technology face challenges with stress-induced deformation and damage due to curing shrinkage of molding and underfilling materials, which compromises the electrical connection reliability of chip stacks.
Innovation Solution
A semiconductor device design incorporating a first seal with a lower elastic modulus than a second seal, where the first seal fills gaps and covers the stack, preventing stress transmission to the semiconductor chips and connection parts, thereby enhancing electrical connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sealing material is used for both underfilling and molding, then the device structure is simplified, but stress-induced deformation and damage occur due to curing shrinkage
Solution Approach 1:
The patent divides the sealing system into two distinct segments: a first seal (underfilling material) filling gaps between chips and a second seal (molding resin) covering the chip stack. This segmentation allows each material to be optimized for its specific function, with the first seal having lower elastic modulus to reduce stress on connections and the second seal providing external protection.
Solution Approach 2:
The patent applies different material properties to different locations within the device. The first seal material is specifically selected to have lower elastic modulus than the second seal material, creating a gradient of mechanical properties that matches the local stress requirements: softer material near fragile connections, harder material for external protection.
2Strength
If molding resin with high elastic modulus is used, then structural strength is improved, but stress transmission to chip connections increases causing damage
Solution Approach 1:
The first seal acts as an intermediary layer between the chip connections and the second seal. It mediates the stress transmission by absorbing and distributing curing shrinkage stresses before they reach the fragile bump electrodes and via electrodes, protecting these connections from damage while still allowing the second seal to provide overall structural strength.
Solution Approach 2:
The first seal provides beforehand cushioning by being positioned between the chips and the second seal, creating a stress-absorbing buffer zone. This cushioning layer is designed with lower elastic modulus to deform preferentially under stress, protecting the chip connections from the full force of curing shrinkage and thermal expansion stresses.
3Object-affected harmful factors
If underfilling material with low elastic modulus is used, then stress on connections is reduced, but the seal becomes less effective at providing structural support
Solution Approach 1:
The patent segments the sealing function into two parts with different mechanical roles. The first seal (underfilling material) with lower elastic modulus specifically addresses stress reduction and gap filling, while the second seal (molding resin) with higher elastic modulus provides the primary structural support and external protection, eliminating the need for the underfilling material to bear structural loads.
4Productivity
If a single seal covers all gaps, then manufacturing steps are reduced, but stress distribution becomes uneven causing connection damage
Solution Approach 1:
The patent segments the sealing application into two distinct steps: first applying the underfilling material to fill gaps between chips and the substrate, then applying the molding resin to cover the entire chip stack. This segmentation enables optimized stress distribution with the softer first seal material in critical gap regions and the harder second seal material providing uniform external coverage.
Data Source
AI summary
A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.


