Semiconductor Chip Stack Stress Absorption via Support Member
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Solution Overview
Problem
The existing semiconductor device of the chip-on-chip (CoC) type experiences stress and cracks due to temperature changes during the manufacturing process, particularly affecting the semiconductor chip with exposed penetration electrodes on the top stage.
Innovation Solution
A semiconductor device configuration where a support member is placed above the top-stage semiconductor chip to absorb stress from penetration electrode expansion or contraction, using a silicon substrate with thermal expansion matching that of the semiconductor chips, and an interface chip to distribute stress, with resin filling gaps to prevent voids and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If penetration electrodes are exposed from the top-stage semiconductor chip surface to enable electrical connection, then electrical interconnection is achieved, but stress concentration and crack generation occur during temperature changes
Solution Approach 1:
A support member is introduced as an intermediary component between the top-stage semiconductor chip and the external environment. This support member receives and distributes the stress generated by penetration electrode expansion/contraction, preventing stress concentration on the chip. The support member acts as a mediator that protects the chip while allowing the penetration electrodes to maintain their electrical connection function.
Solution Approach 2:
The support member is positioned in advance to cushion and absorb the stress that will be generated during temperature changes in the manufacturing process. By having the support member in place before stress occurs, the system prevents crack generation rather than reacting to it after the fact. The support member provides pre-positioned mechanical protection against thermal expansion stresses.
2Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then large-capacity memory is achieved, but stress and crack risk increase in the stacked structure
Solution Approach 1:
The stacked memory system is segmented into multiple functional layers: bottom-stage chips, top-stage chips, and support members interspersed between them. This segmentation allows the support members to specifically address stress issues in the top-stage chips while maintaining the overall stacked structure. The segmentation enables capacity increase through stacking while protecting individual chip integrity through distributed support elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces stress on top-stage semiconductor chips, minimizing cracks and improving thermal conduction and mounting stability, while maintaining manufacturing efficiency and enabling large-capacity memory apparatuses.
Implementation Method 1
using a silicon substrate with thermal expansion matching that of the semiconductor chips
Data Source
AI summary
A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip.