Semiconductor Chip Stack Underfill for Thermal Warpage Control
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Solution Overview
Problem
Multi-chip stacked packages face challenges in heat dissipation and reliability due to thermal expansion, which can lead to warpage and exfoliation at interfaces between materials with different coefficients of thermal expansion.
Innovation Solution
A semiconductor device design that includes an underfill portion with a higher coefficient of thermal expansion than the second semiconductor substrate and a molding portion with an even higher coefficient, both with lower moduli than the substrate, to minimize warpage and exfoliation, along with a thermal interface material and heat sink for enhanced heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip stacked package technology is used to reduce size and increase integration, then device functionality and performance are improved, but heat dissipation becomes more difficult and thermal expansion causes warpage and exfoliation
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between the semiconductor chip and substrate. This underfill material has a coefficient of thermal expansion that matches the semiconductor chip, acting as a buffer that absorbs thermal expansion stress and prevents warpage and exfoliation at the interfaces during temperature cycling
Solution Approach 2:
The patent employs composite material structures including the underfill material combined with molding compound, creating a multi-layer composite package structure. The underfill layer (with specific CTE matching the chip) is combined with the molding compound (with different CTE properties) to distribute and manage thermal stresses across the package, improving overall thermal expansion resistance
2Area of stationary object
If multi-chip stacked package technology is used to reduce size, then package footprint is reduced, but heat dissipation efficiency deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional single-chip layout to a three-dimensional stacked package architecture. Multiple semiconductor chips are vertically stacked and interconnected through through-silicon vias (TSVs), enabling high-density integration in a small footprint while providing multiple thermal pathways through the stack to improve heat dissipation efficiency
3Adaptability or versatility
If through vias are used to connect stacked chips, then electrical connectivity is improved, but structural stability under thermal stress deteriorates
Solution Approach 1:
The underfill material serves as a mediator that mechanically supports the stacked chip structure and compensates for thermal expansion mismatches. This prevents stress concentration at the through via interfaces during thermal cycling, maintaining structural stability while preserving electrical connectivity through the via structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces warpage and exfoliation risks while improving heat dissipation, ensuring the reliability and performance of multi-chip stacked packages.
Implementation Method 1
an underfill portion 28 covering a space between the first semiconductor chip 10 and the second semiconductor chip 20 and covering sidewalls 30 of the second chip 20, and a molding portion 29 separated from the second chip 20 by the underfill portion 28
Implementation Method 2
a thermal interface material and heat sink for enhanced heat dissipation
Data Source
AI summary
A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.