Semiconductor Chip Stacking With Substrate Grooves To Reduce Warpage

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Solution Overview

Problem

The challenge in semiconductor device fabrication is warpage in stacked semiconductor chips, which complicates encapsulation, interconnection formation, and reduces productivity, making it difficult to align electrodes with the substrate, thereby hindering improved productivity.

Innovation Solution

The method involves creating a substrate with intersecting grooves to reduce warpage by using grooves on the substrate to align and stack semiconductor chips, providing an encapsulation layer, and cutting the encapsulation along these grooves to enhance alignment and cutting accuracy, ensuring precise positioning and integration of semiconductor chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor chips are stacked to increase capacity and functionality, then the device capacity and functionality are improved, but warpage is generated in the stacked body making encapsulation and interconnection formation difficult

Engineering Contradiction:
Improvedevice capacityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The substrate is divided into multiple regions by grooves, and semiconductor chips are stacked on each region separately. This segmentation allows independent control of each stacking region, preventing warpage propagation across the entire substrate and maintaining alignment precision during encapsulation and interconnection formation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are used for different stacking operations, with each region having optimized local properties. The grooves create localized zones where chips can be stacked with controlled warpage characteristics, while other regions remain flat for precise alignment operations

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If semiconductor chips are stacked on the substrate, then the device capacity is improved, but warpage makes it difficult to align electrodes of the chips with electrodes on the substrate

Engineering Contradiction:
Improvedevice capacityVSAvoidalignment accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

Grooves are formed on the substrate before stacking semiconductor chips. This preliminary action creates a structured foundation that prevents warpage during the stacking process, ensuring that electrodes remain properly aligned with substrate electrodes from the beginning of the stacking operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The problem of warpage in the stacking direction (vertical dimension) is addressed by introducing grooves in the horizontal plane. This dimensional approach allows control of vertical alignment issues through horizontal structural features, maintaining electrode alignment accuracy

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If warpage is generated in the stacked body, then encapsulation and interconnection formation become difficult, but productivity decreases

Engineering Contradiction:
Improveencapsulation qualityVSAvoidfabrication productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By dividing the substrate into segmented regions with grooves, warpage is confined to localized areas rather than affecting the entire stacked body. This allows encapsulation and interconnection formation to proceed efficiently on flat regions while maintaining high reliability in the segmented stacking regions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The grooves act as intermediary structures between the substrate and stacked chips, providing a transition zone that prevents warpage propagation. This intermediary structure enables both high encapsulation quality and maintained productivity by allowing standard fabrication processes to continue

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10128153B2Method of fabricating a semiconductor device and the semiconductor device
Publication Date: 2018.11.13 KK TOSHIBA
  • US10128153B2 patent drawing
  • US10128153B2 patent drawing
  • US10128153B2 patent drawing

AI summary

a method of fabricating a semiconductor device is described below.The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves.The device and the method can provide higher productivity.