Semiconductor Chip Stacking via Via Holes and Insulating Layers
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Solution Overview
Problem
Conventional semiconductor device manufacturing methods face challenges such as low productivity, increased costs, and reliability issues due to complex processes involving deep via holes, material variations, and the need for specialized processes to stack multiple semiconductor substrates or chips.
Innovation Solution
A semiconductor device manufacturing method that involves forming a first insulating layer on a semiconductor substrate, disposing semiconductor chips with integrated circuits on top, creating via holes through these chips, and connecting them with metal layers to enable signal transmission between layers, allowing for efficient stacking and connection of multiple semiconductor chips without the need for bumps or deep via holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional WOW or COW methods are used to stack semiconductor substrates or chips, then three-dimensional integration is achieved, but the process complexity increases and productivity decreases due to deep via holes and specialized processes
Solution Approach 1:
The invention performs thickness reduction of the first substrate before bonding, and forms via holes in the second substrate after bonding. This preliminary action on the first substrate enables easier via hole formation and eliminates the need for deep via holes that would require complex specialized processes, thereby improving productivity while achieving three-dimensional integration
Solution Approach 2:
The invention divides the substrate processing into distinct stages: thickness reduction of the first substrate before bonding, bonding of substrates, and via hole formation in the second substrate after bonding. This segmentation allows each process to be optimized independently, avoiding the need for complex deep via hole processes and improving overall manufacturing productivity
2Reliability
If deep via holes are formed to connect stacked substrates or chips, then electrical connection is achieved, but manufacturing costs increase and reliability decreases due to material variations
Solution Approach 1:
The invention performs thickness reduction of the first substrate before bonding to a thinner substrate. This preliminary thinning creates a configuration where via holes can be formed more easily in the second substrate after bonding, eliminating the need for deep via holes and specialized processes, thereby improving ease of manufacture while maintaining reliable electrical connections
Solution Approach 2:
Instead of forming via holes through the first substrate after bonding (which would require deep via holes), the invention forms via holes in the second substrate after bonding. This inverted approach exploits the thinner profile of the second substrate to achieve easier via hole formation and more reliable electrical connections with fewer materials
3Volume of moving object
If specialized processes are used to stack multiple semiconductor substrates or chips, then multi-layer integration is achieved, but device complexity increases
Solution Approach 1:
The invention performs thickness reduction of the first substrate before bonding, which simplifies subsequent via hole formation in the second substrate. This preliminary action eliminates the need for complex deep via hole processes and specialized stacking procedures, thereby reducing device complexity while achieving multi-layer integration
Solution Approach 2:
The invention segments the stacking process into simple, sequential steps: thickness reduction of first substrate, bonding, and via hole formation in second substrate. This segmentation avoids complex specialized processes and enables multi-layer integration through straightforward, repeatable operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances productivity and reduces manufacturing costs by simplifying the process, improving the reliability of electrical connections, and enabling the stacking of multiple semiconductor substrates or chips while maintaining high signal transmission efficiency.
Implementation Method 1
forming a first insulating layer on a main surface of a first semiconductor substrate
Implementation Method 2
forming a metal layer in each of the via holes to connect the semiconductor chips to one another
Data Source
AI summary
A semiconductor device manufacturing method of stacking semiconductor chips in layers over a semiconductor substrate having, close to its main surface, semiconductor chips, connecting semiconductor chips in different layers to enable signal transmission, and singularizing the layered semiconductor chips into pieces. The method includes steps of forming an insulating layer on the main surface of the semiconductor substrate; stacking the semiconductor chips over the semiconductor chips of the semiconductor substrate in such a manner as to interpose the insulating layer between them and an opposite surface of each disposed semiconductor chip opposes the insulating layer, the opposite surface being opposite to the main surface; forming, in each of the disposed semiconductor chips, a via hole penetrating from the main to the opposite surface; and forming a connection which enables signal transmission between the disposed semiconductor chips and the corresponding semiconductor chips of the semiconductor substrate via the via holes.