Semiconductor Chip Stress Absorption Structure for Antenna Integration
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Solution Overview
Problem
The integration of antenna and logic circuits on a semiconductor chip leads to significant stress during manufacturing processes, causing delamination of interlayer dielectric layers in the peripheral region, which affects power consumption and transmission efficiency.
Innovation Solution
Incorporating a stress absorption structure within the interlayer dielectric layers in the peripheral region, electrically connected to the transmission pattern, which absorbs stress generated during patterning and curing processes, and allows for impedance matching to improve transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the antenna is integrated on the semiconductor chip, then the power consumption is significantly decreased, but the thermal or mechanical actions during wafer manufacturing process cause huge stress that results in delamination of the interlayer dielectric layers
Solution Approach 1:
A stress absorption structure is introduced as an intermediary element between the antenna and the interlayer dielectric layers. This structure specifically absorbs thermal or mechanical stress generated during wafer manufacturing processes, preventing stress transmission to the interlayer dielectric layers and avoiding delamination, while allowing the antenna integration benefits to be maintained
Solution Approach 2:
The stress absorption structure converts the harmful stress that would cause delamination into a beneficial stress-dissipating mechanism. By deliberately incorporating this structure, the harmful thermal or mechanical actions during manufacturing are transformed into a controlled stress absorption process that protects the interlayer dielectric layers while maintaining antenna functionality
Data Source
AI summary
A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.