Semiconductor Chip Thinning via Etch Stop Layer
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Solution Overview
Problem
The increasing demand for smaller, lighter, and more powerful electronic devices with higher power densities, particularly in electrical converter devices, necessitates the minimization of energy losses due to electrical resistances, which is challenging in existing semiconductor manufacturing processes.
Innovation Solution
A method for manufacturing semiconductor devices involves selectively removing semiconductor chips at one main face to reduce thickness, using techniques like etching with an etch stop layer and encapsulation, while maintaining structural integrity and functionality, particularly for vertical power transistors, to decrease on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor chip thickness is reduced to decrease on-resistance, then the on-resistance decreases and energy conversion efficiency improves, but the structural integrity and mechanical strength of the device deteriorate
Solution Approach 1:
An etch stop layer is formed at a predetermined depth within the semiconductor chip before any thinning operations. This pre-formed layer acts as a mechanical reinforcement that prevents the chip from becoming too thin and losing structural integrity, while still allowing the chip to be thinned enough to reduce on-resistance.
Solution Approach 2:
The etch stop layer serves as an intermediary structural element between the front and back surfaces of the semiconductor chip. It provides mechanical support and prevents through-etching or excessive thinning, enabling the chip to maintain sufficient strength while being thinned to reduce resistance.
2Loss of energy
If the semiconductor chip is thinned to reduce on-resistance, then the on-resistance decreases, but the risk of chip breakage and manufacturing defects increases
Solution Approach 1:
The etch stop layer is formed in advance at a controlled depth, creating a safety barrier that prevents the chip from being etched too thin. This preliminary structural reinforcement reduces the risk of chip breakage during subsequent manufacturing steps while still allowing sufficient thinning to reduce on-resistance.
Solution Approach 2:
The etch stop layer acts as a cushioning barrier that prevents over-etching and excessive thinning. By having this protective layer in place before thinning operations, the manufacturing process becomes more reliable and less prone to defects caused by chips becoming too thin or breaking.
3Length of moving object
If selective removal of semiconductor material is performed to reduce chip thickness, then the on-resistance decreases and device compactness improves, but the manufacturing process complexity increases
Solution Approach 1:
The semiconductor chip is segmented into different regions with different doping concentrations, creating an etch stop layer at a specific depth. This segmentation allows selective removal of material from the back surface while the etch stop layer region remains intact, enabling controlled thinning without through-etching.
Solution Approach 2:
The doping concentration parameter is changed to create the etch stop layer, which has different etching characteristics than the surrounding semiconductor material. This parameter change enables selective removal of material at controlled rates, simplifying the thinning process by providing a natural stop point that prevents over-etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of thinner semiconductor devices with reduced on-resistance, enhancing energy conversion efficiencies and supporting the development of more compact, high-performance electronic devices.
Implementation Method 1
An etch stop layer is formed in the semiconductor chip at a pre-defined depth from the first main face
Data Source
AI summary
The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.