Semiconductor Chip Through Electrode Stacked Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face challenges in achieving high capacity, high speed, and high reliability while maintaining a compact and lightweight design, particularly in stacked structures where signal delays and loading effects due to parasitic capacitance can hinder performance.
Innovation Solution
The semiconductor package incorporates a semiconductor chip with a through electrode, inter-mediation pad, and rewiring line, allowing for efficient signal transmission and connection to external terminals, reducing signal failure and imbalance by optimizing the wiring structure and using a stacked chip configuration with wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked structure with multiple semiconductor chips is used to increase capacity, then the storage capacity increases, but signal delays and loading effects due to parasitic capacitance worsen
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacked mounting of semiconductor chips. Multiple chips are arranged vertically in stacks, with lower chips mounted on the PCB and upper chips mounted on lower chips. This vertical arrangement increases storage capacity while the through-electrode structure maintains signal integrity by providing direct electrical pathways through the chip stack, reducing parasitic capacitance effects.
Solution Approach 2:
The patent introduces through-electrodes as intermediary elements that penetrate through the semiconductor chips to establish direct electrical connections between upper and lower chips. These through-electrodes act as mediators that reduce signal delays and loading effects by providing low-inductance, low-capacitance pathways, thereby maintaining signal integrity in the stacked configuration.
2Weight of stationary object
If the semiconductor chip size is reduced to make the package smaller and lighter, then the package size and weight decrease, but maintaining high reliability and performance becomes more difficult
Solution Approach 1:
The patent employs vertical stacking to increase capacity without increasing the planar footprint. By arranging chips in three-dimensional stacks rather than spreading them out in two dimensions, the package achieves higher capacity in a smaller, lighter form factor while maintaining signal reliability through the through-electrode connection structure.
3Ease of operation
If wiring connections are extended to connect distant pads, then all connections can be established, but signal delays and loading effects increase
Solution Approach 1:
The through-electrodes serve as intermediary connection elements that provide direct, short electrical pathways through the chip stack. Instead of using long external wiring to connect pads on different chips, the through-electrodes create compact internal connections that minimize signal path length, reducing delays and loading effects while maintaining complete connectivity.
Solution Approach 2:
The patent moves wiring connections from the external planar dimension to the internal vertical dimension by using through-electrodes that penetrate through the chip thickness. This three-dimensional wiring approach shortens connection paths compared to traditional planar wiring, improving signal speed while maintaining connection completeness.
Data Source
AI summary
A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.