Semiconductor Chip Vapor Deposition Encapsulation

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Solution Overview

Problem

Semiconductor devices are prone to damage during production and operation, and existing manufacturing methods are costly and inefficient, necessitating improved quality and cost reduction.

Innovation Solution

The method involves depositing thin material layers, such as organic materials or polymers like parylene, over semiconductor chips using techniques like vapor deposition, spray coating, or dip coating to encapsulate and protect the chips, which can be directly applied after dicing, simplifying the process and enhancing protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional manufacturing methods are used, then semiconductor devices can be produced, but they are prone to damage during production and operation and production costs are high

Engineering Contradiction:
Improvedamage resistanceVSAvoidproduction cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by depositing a protective material layer on the semiconductor chip before dicing. This pre-coating approach ensures that the protective layer is already in place before the chip undergoes the damaging dicing process, thereby preventing damage during production while maintaining cost-effectiveness through a simplified process flow

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective material layer serves as a cushioning layer that absorbs mechanical stresses and damages during dicing and subsequent handling. By placing this protective layer beforehand, the chip is cushioned against damage during production and operation, improving reliability without adding complex manufacturing steps

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If protective layers are applied after dicing, then chip damage is reduced, but manufacturing complexity and costs increase

Engineering Contradiction:
Improvechip protectionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reverses the conventional sequence by applying the protective material layer before dicing rather than after. This preliminary action simplifies the manufacturing process by eliminating the need for post-dicing coating operations, reducing manufacturing complexity while maintaining effective chip protection

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the protective coating step with the pre-dicing preparation process. By combining these operations into a single pre-dicing step, the manufacturing process becomes less complex and more efficient, avoiding the need for separate post-dicing coating operations

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces damage to semiconductor devices, improves manufacturing efficiency, and lowers production costs by providing a protective barrier against environmental influences while allowing direct post-dicing coating, enabling batch processing and cost-effective production.

Implementation Method 1

depositing thin material layers, such as organic materials or polymers like parylene, over semiconductor chips using techniques like vapor deposition

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Implementation Method 2

depositing thin material layers, such as organic materials or polymers like parylene, over semiconductor chips using techniques like spray coating

Methodology Applied
Scientific EffectSpray coating: Fluid Spray

Data Source

PatentUS9576872B2Semiconductor devices and methods for manufacturing semiconductor devices
Publication Date: 2017.02.21 INFINEON TECHNOLOGIES AG
  • US9576872B2 patent drawing
  • US9576872B2 patent drawing
  • US9576872B2 patent drawing

AI summary

A method includes arranging multiple semiconductor chips over a first carrier and depositing a first material layer over surfaces of the multiple semiconductor chips, wherein depositing the first material layer includes a vapor deposition, and wherein the first material layer includes at least one of an organic material and a polymer.