Radiation-Emitting Semiconductor Chip Vertical Isolation
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Solution Overview
Problem
Radiation-emitting semiconductor chips face challenges in electrical isolation of their epitaxial semiconductor layer sequences from the backside, leading to potential leakage currents due to metal impurities and structural instability.
Innovation Solution
A semiconductor chip design incorporating a carrier with a pn-junction and a vertical region that is n-doped or p-doped, combined with a dielectric and metallic layer, forms a self-locking MOSFET or electrically insulating structure to effectively isolate the epitaxial semiconductor layer sequence from the backside, reducing leakage currents and enhancing mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the epitaxial semiconductor layer sequence is made thin to reduce device complexity, then manufacturing precision is improved, but electrical isolation from the backside deteriorates due to potential leakage currents
Solution Approach 1:
A vertical region filled with dielectric material is introduced as an intermediary barrier between the epitaxial semiconductor layer sequence and the backside of the carrier. This dielectric-filled vertical region acts as an electrical insulator that prevents leakage currents while allowing the epitaxial layer to remain thin for precise manufacturing control.
Solution Approach 2:
The carrier structure is designed as a composite system combining silicon (or silicon carbide) carrier material with dielectric material in the vertical region. This composite structure provides both mechanical support from the carrier and electrical isolation from the dielectric-filled vertical region, resolving the contradiction between thin layer precision and electrical isolation reliability.
2Strength
If the carrier thickness is increased to improve mechanical stability, then strength is improved, but electrical isolation from the backside deteriorates due to longer conduction paths
Solution Approach 1:
The vertical region is positioned specifically at the boundary region of the carrier where electrical isolation is most critical. By concentrating the dielectric material in this local area rather than throughout the entire carrier thickness, the solution provides effective electrical isolation while maintaining the carrier's overall mechanical strength through its full thickness.
3Reliability
If a pn-junction is formed in the carrier to improve electrical isolation, then reliability is improved, but device complexity increases due to additional doping regions
Solution Approach 1:
Instead of relying solely on complex pn-junction doping patterns to achieve electrical isolation, the invention extracts the isolation function into a separate dielectric-filled vertical region. This separation simplifies the carrier structure by removing the need for complex vertical doping profiles while maintaining effective electrical isolation through the physical barrier of the dielectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides robust electrical isolation and reduced leakage currents, ensuring high-current performance with low lead-in resistance and improved manufacturing ease by using a self-locking MOSFET or electrically insulating vertical region within the semiconductor chip.
Implementation Method 1
The carrier has an n-doped layer and a p-doped layer that form a pn junction. Usually, a blocking direction of the pn-junction runs from the first main surface of the carrier to the second main surface of the carrier. The pn-junction isolates the epitaxial semiconductor layer sequence at least within a central volume region of the carrier from the backside of the semiconductor chip.
Implementation Method 2
the vertical region is electrically insulating and penetrates the pn-junction of the carrier. Also in this way, leakage currents over the side faces of the carrier can be at least reduced with advantage and the backside of the semiconductor chip can be electrically isolated against the epitaxial semiconductor layer sequence particularly effectively.
Data Source
AI summary
A radiation emitting semiconductor chip is disclosed. In an embodiment, a radiation-emitting semiconductor chip includes a carrier including a first main surface and a second main surface opposite to the first main surface, an n-doped layer and a p-doped layer forming a pn-junction and a vertical region starting from the first main surface and running parallel to side faces of the carrier, wherein the vertical region is n-doped, p-doped or electrically insulating, and wherein the vertical region extends within a boundary region of the carrier and completely encloses a central volume region of the carrier, an epitaxial semiconductor layer sequence having an active zone configured to generate electromagnetic radiation during operation, the epitaxial semiconductor layer sequence being located at the first main surface of the carrier and two electrical contacts disposed on a front side of the semiconductor chip.