Semiconductor Structure for Dense Chip-to-Chip Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in connecting the densely packed contacts between the array and periphery regions of chips, which limits chip size reduction and increases costs due to the complexity of electrical connections in conventional chip designs.
Innovation Solution
The approach involves fabricating an array chip with vias that are independently formed and then assembled to a periphery chip, utilizing conductive pads for improved electrical connections, thereby enhancing the reliability and stability of chip-to-chip connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the chip size is reduced and feature size is shrunk, then the density of word lines and bit lines is increased, but the distances between contacts at the ends of word lines and bit lines become very small making it difficult to connect those contacts to other chips
Solution Approach 1:
The chip is divided into two separate chips: an array chip containing the memory array with word lines and bit lines, and a periphery chip containing the peripheral circuits. This segmentation allows each chip to be optimized independently, with the array chip having smaller feature sizes for higher density while the periphery chip can have larger contact areas for easier connection, thus resolving the contradiction between increased density and ease of connection.
2Area of stationary object
If the distances between contacts are decreased to increase density, then the area required for setting contacts is reduced, but the possibility of short circuit increases and connection reliability decreases
Solution Approach 1:
By separating the array and periphery regions onto different chips, the contacts on the array chip can be densely packed for high density, while the connection interface is established through multiple vias and conductive pads that provide reliable electrical connection without requiring large distances between individual contacts, thus maintaining both high density and connection reliability.
Solution Approach 2:
Multiple vias and conductive pads are introduced as intermediary structures between the word lines/bit lines and the periphery chip. These intermediaries distribute the electrical connection across multiple points, reducing the risk of short circuits while maintaining reliable connections, thus resolving the contradiction between compact contact spacing and connection reliability.
3Ease of manufacture
If the array region and periphery region are fabricated together on the same chip, then the manufacturing process is simpler, but the total cost increases due to the inability to remove the Cpa×Ap and Cpp×Aa cost components
Solution Approach 1:
The manufacturing process is segmented into two independent fabrication processes: one for the array chip and another for the periphery chip. This allows each chip to be manufactured separately with optimized processes, and the cost components Cpa×Ap and Cpp×Aa are eliminated since the array region is no longer fabricated on the periphery chip substrate. The separate chips are then connected through vias, achieving cost reduction while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.