Semiconductor Chip Wiring Configuration for Reduced Package Size
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Solution Overview
Problem
In multi-chip semiconductor packages using the TSV method, the re-distribution layer's wiring resistance and package size are increased due to the need for multiple wirings for power and ground voltages, leading to longer wiring lengths and increased capacitance and inductance, which complicates design and increases package size.
Innovation Solution
The semiconductor device configuration includes two wirings for identical power or ground voltages with one terminal on the package substrate and two terminals on the interface or core chip side, allowing for shorter wirings and reduced package size by decreasing the number of large-sized bumps on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wirings are provided for identical power or ground voltages in the re-distribution layer, then wiring resistance is reduced, but wiring length increases leading to increased capacitance and inductance
Solution Approach 1:
The patent transitions from planar wiring layout to three-dimensional vertical wiring through TSVs. Multiple wirings for identical voltages are routed through different vertical levels and TSV paths, reducing their lateral length and associated capacitance/inductance while maintaining parallel configuration for low resistance.
Solution Approach 2:
The re-distribution layer is divided into multiple hierarchical levels with TSVs connecting different chip layers. Power and ground wirings are segmented across these levels, allowing parallel paths that reduce resistance while the vertical segmentation shortens effective wiring length compared to single-layer routing.
2Reliability
If multiple wirings for identical voltages are provided, then wiring resistance decreases, but package size increases
Solution Approach 1:
The patent utilizes vertical stacking with TSVs to route multiple power and ground wirings through the thickness dimension rather than spreading them laterally. This three-dimensional wiring approach reduces the planar footprint required for multiple parallel wirings, thereby reducing package size while maintaining low resistance through parallel paths.
3Area of stationary object
If the number of large-sized bumps on the substrate is reduced, then package size decreases, but the ability to provide multiple wirings for identical voltages is compromised
Solution Approach 1:
The patent implements nested wiring structures where multiple wiring layers are stacked vertically and connected through TSVs. This nested configuration allows multiple parallel power and ground paths to be contained within a compact vertical space, reducing the need for large substrate bumps while maintaining low resistance through the nested parallel pathways.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first surface of the first semiconductor chip; a first terminal connected to one end of the first wiring and one end of the second wiring, and connected to an outside; a second terminal connected to the other end of the first wiring; and a third terminal connected to the other end of the second wiring, and connected to the second terminal.