Semiconductor Circuit Layout with Closed Loop Dummy Patterns
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Solution Overview
Problem
In semiconductor circuit structures, large distances between circuit patterns lead to stress concentration at junctions with insulating areas, potentially disrupting or distorting the circuit patterns during manufacturing.
Innovation Solution
A layout method that involves placing closed loop dummy patterns between adjacent circuit patterns, which are electrically insulated from the circuit patterns, to redistribute stress and enhance mechanical strength, and optionally includes additional dummy patterns or vacancies to manage stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large distances are maintained between circuit patterns to prevent contact, then electrical insulation is improved, but stress concentration occurs at junctions with insulating areas
Solution Approach 1:
The patent introduces dummy patterns as intermediary elements between circuit patterns. These dummy patterns serve as stress-absorbing mediators that prevent direct stress concentration at the junctions between circuit patterns and insulating areas, while maintaining the electrical insulation function of the large distances between circuit patterns.
Solution Approach 2:
The patent applies beforehand cushioning by placing dummy patterns in advance in regions where stress concentration is expected to occur. These dummy patterns act as pre-positioned cushioning elements that absorb manufacturing stresses before they can damage the circuit patterns, particularly in areas with large distances between circuit patterns.
2Productivity
If circuit patterns are placed closer together to increase integration level, then productivity is improved, but risk of stress-induced disruption increases
Solution Approach 1:
The dummy patterns act as intermediary stress-absorbing elements that protect circuit patterns from manufacturing stresses. This allows circuit patterns to be placed closer together for higher integration while the dummy patterns absorb the stresses that would otherwise disrupt the closely-spaced patterns.
Solution Approach 2:
The patent changes the physical parameters of the circuit structure by adding dummy patterns with specific geometries and materials. This modifies the stress distribution parameters in the overall structure, allowing closer spacing of functional circuit patterns while maintaining their integrity through the altered stress field created by the dummy patterns.
3Reliability
If dummy patterns are added to mitigate stress, then pattern integrity is improved, but device complexity increases
Solution Approach 1:
The dummy patterns are essentially non-functional, sacrificial elements that serve only to absorb stress. They are 'cheap' in the sense that they don't need to perform any functional circuit role, and their only purpose is to protect the functional circuit patterns during manufacturing. This allows significant complexity reduction compared to trying to make the functional patterns themselves stress-resistant.
Solution Approach 2:
The patent segments the circuit layout into functional circuit patterns and non-functional dummy patterns. This segmentation allows the functional patterns to be optimized for circuit performance while the dummy patterns handle the mechanical stress protection function, reducing overall complexity by separating concerns.
Data Source
AI summary
A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.