Semiconductor Circuit Parasitic Extraction Segmentation
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Solution Overview
Problem
The increasing complexity of semiconductor circuit design at advanced technology nodes leads to a conflict between achieving accurate parasitic parameter extraction and processing speed during RC extraction, as the large amount of data to be processed slows down the extraction process while sacrificing accuracy.
Innovation Solution
The proposed solution involves dividing the semiconductor circuit into functional and loading areas, where parasitic parameters of devices and signal lines are extracted in functional areas, and only signal line parameters are extracted in loading areas, reducing data handling and improving processing speed without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If parasitic parameters of all devices and signal lines are extracted in the entire circuit, then extraction accuracy is improved, but processing time increases significantly
Solution Approach 1:
The circuit is divided into functional areas and loading areas. In functional areas, parasitic parameters of both devices and signal lines are extracted to ensure accuracy. In loading areas, only signal line parasitic parameters are extracted, reducing processing time. This segmentation allows different extraction depths in different circuit regions, resolving the contradiction between accuracy and speed.
Solution Approach 2:
Different extraction strategies are applied to different regions of the circuit based on their functional importance. Functional areas receive full extraction treatment while loading areas receive simplified treatment. This local differentiation optimizes the balance between extraction accuracy and processing time by concentrating resources where they are most needed.
2Productivity
If circuit density is increased at advanced technology nodes, then functionality and speed are improved, but data processing complexity increases
Solution Approach 1:
The high-density circuit is segmented into functional and loading areas, allowing the extraction tool to focus computational resources on critical functional regions while using simplified models in loading areas. This reduces the overall data processing complexity while maintaining the benefits of advanced technology node density.
Solution Approach 2:
The extraction approach changes parameters based on location: full device and signal line parameters are extracted in functional areas, while only signal line parameters are extracted in loading areas. This parameter differentiation reduces data processing complexity in low-criticality regions without affecting circuit performance.
Data Source
AI summary
A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.