Semiconductor Circuit Layout Pattern Replacement
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Solution Overview
Problem
Conventional methods for modifying semiconductor circuit designs often result in unnecessary or unintended modifications when addressing problematic element patterns, leading to potential defects in the final circuit layout.
Innovation Solution
A pattern-based approach is employed, where specific problematic element patterns in a circuit design layout are identified and replaced with corresponding replacement patterns, using libraries stored in a storage medium and processed by a computer, ensuring local modifications that maintain boundary characteristics and avoid global rule changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global rule change is applied to modify problematic element patterns across the entire circuit design layout, then printability problems are addressed, but unnecessary or unintended modifications occur at various locations within the circuit design layout
Solution Approach 1:
The patent implements local rule changes by identifying specific problematic element patterns through pattern matching and applying modifications only to those identified instances. The system compares element patterns in the circuit design layout against a library of known problematic patterns, and applies rule changes locally to matching patterns rather than globally across the entire layout. This resolves the contradiction by addressing printability issues only where they exist without causing unintended modifications elsewhere in the design.
Solution Approach 2:
The patent segments the circuit design layout into individual element patterns that can be independently analyzed and modified. By breaking down the layout into discrete patterns and applying rule changes to specific segmented instances rather than the entire layout, the system addresses printability problems locally while preserving the integrity of other circuit elements. This segmentation approach prevents the propagation of unintended modifications across the entire design.
2Reliability
If multiple simulations are performed to improve functional and yield characteristics of the circuit design layout, then circuit performance is optimized, but simulation time increases
Solution Approach 1:
The patent performs preliminary pattern matching and identification of problematic element patterns before conducting full circuit simulations. By pre-identifying and correcting printability issues through pattern matching against a library of known problematic patterns, the system eliminates defects that would otherwise require multiple iterative simulations to detect and fix. This preliminary action reduces the need for repeated simulations, thereby optimizing yield characteristics while reducing simulation time.
Data Source
AI summary
Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.