Semiconductor Circuit Floating Node Refresh Signal Stability
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Solution Overview
Problem
Existing semiconductor circuits face issues with fluctuations in transistor characteristics, leading to circuit malfunctions and increased complexity due to leakage currents and variations in transistor characteristics, particularly when using thin-film transistors on glass substrates.
Innovation Solution
A semiconductor circuit design that incorporates a refresh signal with a period shorter than the clock signal to actively manage floating nodes, improving operational margins without increasing the number of clock signals, and utilizing a shift register circuit with cascade-connected stages to generate output signals in response to control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin-film transistors are used on glass substrates, then manufacturing cost is reduced and integration is improved, but transistor characteristic fluctuations increase leading to circuit malfunctions
Solution Approach 1:
The patent applies preliminary action by introducing a refresh signal before the clock signal to pre-charge floating nodes to a predetermined potential. This preliminary charging action ensures that when the clock signal activates the circuit, the floating nodes are already stabilized, preventing malfunctions due to transistor characteristic fluctuations. The refresh signal is generated in advance and applied to nodes that will become floating during circuit operation.
Solution Approach 2:
The patent implements beforehand cushioning by providing a refresh circuit that actively maintains floating nodes at a stable potential before they are needed for normal operation. This cushioning effect compensates for the inherent instability of thin-film transistors on glass substrates by pre-establishing safe operating conditions. The refresh circuit acts as a protective mechanism that prevents circuit malfunctions before they can occur.
2Device complexity
If floating nodes are managed without refresh signals, then device complexity is reduced, but abnormal outputs increase due to potential changes
Solution Approach 1:
The patent applies universality by designing the refresh circuit to share the same signal lines and transistors with the main shift register circuit wherever possible. The refresh signal utilizes the existing clock signal generation infrastructure, and the refresh transistors are integrated into the same circuit layer. This multi-functional approach minimizes additional complexity while providing the necessary refresh functionality to stabilize floating nodes.
3Reliability
If the refresh signal period is made shorter than the clock signal period, then floating node stability is improved, but signal timing complexity increases
Solution Approach 1:
The patent applies dynamics by making the refresh signal timing adaptable to the circuit operation cycle. The refresh signal is generated with a period that is intentionally shorter than the clock signal period, allowing it to complete its charging function before the main circuit operation begins. This dynamic timing relationship ensures that floating nodes are always refreshed in advance, regardless of the specific operating conditions, while maintaining a simple and predictable timing structure.
Data Source
AI summary
In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.