Semiconductor Memory Clock Generator Using Divided-Clock Phase Correction
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Solution Overview
Problem
High-speed semiconductor memory apparatuses face challenges in correcting clock phases and reliability due to shortening clock periods, leading to frequent clock errors and reduced system performance.
Innovation Solution
A clock generator with a first and second divider, delay units, duty-cycle corrector, phase comparator, and delay time setting unit, which divides and delays internal clocks, corrects duty cycles, and adjusts delay times to stabilize and synchronize clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of the semiconductor memory apparatus is increased, then the productivity is improved, but the clock period becomes shorter making phase correction difficult and clock errors frequent
Solution Approach 1:
The delay element array is divided into multiple banks (first bank, second bank, etc.), each handling different delay ranges. This segmentation allows for more precise and faster phase correction by selecting appropriate banks based on the required delay, enabling reliable clock generation even at high operation speeds where the overall clock period is short.
Solution Approach 2:
The delay element array uses dynamically selectable delay elements controlled by control signals. The system can adaptively adjust which delay elements are active based on real-time phase error feedback from the phase comparator, enabling fast convergence and stable clock generation at high speeds where static delay configurations would be insufficient.
2Productivity
If the operation speed of the semiconductor memory apparatus is increased, then the productivity is improved, but the phase correction becomes difficult leading to frequent clock errors
Solution Approach 1:
By segmenting the delay element array into multiple banks with different delay ranges, the system can quickly identify and correct phase errors without requiring extensive search through all possible delay values. This segmentation makes phase correction more manageable and reliable at high operation speeds.
Solution Approach 2:
The phase comparator continuously monitors the phase relationship between the delayed clock signal and the reference clock, providing real-time feedback to control the selection of delay elements. This feedback mechanism enables automatic and rapid phase correction, making the system easy to operate even at high speeds where manual or slow correction would fail.
3Device complexity
If a traditional DLL structure is used, then the device complexity is reduced, but the clock reliability is lowered due to frequent errors at high speeds
Solution Approach 1:
The delay element array is segmented into multiple banks, each containing delay elements with different delay characteristics. This segmentation increases the precision and range of phase correction capability, significantly improving clock reliability at high speeds while maintaining a relatively simple overall DLL structure that builds upon the traditional architecture.
Solution Approach 2:
The system changes the delay parameter by selecting different delay elements from different banks based on the required phase correction amount. This parameter adjustment capability allows the system to adapt to various operating conditions and maintain high clock reliability across different speed ranges without fundamentally changing the DLL structure.
Data Source
AI summary
The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clock generator for semiconductor memory apparatus exactly performs phase correction and duty cycle correction using frequency-divided clocks. Therefore, it is possible to generate reliable clocks and to improve the operational performance of a system using the clock generator.