Semiconductor Device Clock Gating for Zero-Valued Systolic Data
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Solution Overview
Problem
Semiconductor devices with systolic arrays experience high power consumption due to operations on input data containing a high number of O-valued elements, as once the data is in the input stream, operations are performed without consideration for zero-valued elements.
Innovation Solution
Implementing clock-gated registers and logic elements that deactivate when zero-valued bits are detected, reducing operations and power consumption by selectively gating registers and logic elements during clock cycles where zero-valued data is present.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If systolic arrays perform operations on all input data elements, then processing completeness is maintained, but power consumption increases due to operations on zero-valued elements
Solution Approach 1:
The patent implements dynamic control of processing elements based on data values. Clock gating mechanisms dynamically enable or disable processing elements depending on whether input data contains zero-valued elements, allowing the system to adapt its operational state to match the actual computational requirements of the input data
Solution Approach 2:
The patent applies different operational states to different processing elements based on local data characteristics. When zero-valued elements are detected in specific input streams, only the corresponding processing elements are deactivated, while other processing elements continue normal operations, achieving localized optimization without affecting overall system functionality
2Loss of energy
If clock-gated registers and logic elements are implemented, then power consumption is reduced by deactivating zero-valued operations, but device complexity increases
Solution Approach 1:
The patent segments the systolic array into independent processing elements, each with its own clock-gated registers and logic elements. This segmentation allows selective deactivation of individual processing elements based on their input data, enabling power savings without requiring complex system-wide control mechanisms
Solution Approach 2:
Each processing element incorporates self-service clock gating control that automatically detects zero-valued input elements and deactivates its own operations accordingly. This self-service mechanism eliminates the need for complex external control logic, reducing overall device complexity while achieving power savings
Data Source
AI summary
A device includes a first register, a second register, a third register and a first logic element. The first register is configured to store first input data. The second register is configured to store first weight data. The third register is configured to output first output data according to each of the first input data and the first weight data. The first logic element is configured to control the first register according to each of first bit data and second bit data. The first bit data and the second bit data correspond to the first input data and the first weight data, respectively.