Semiconductor Device Internal Clock Generation Circuit
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Solution Overview
Problem
Semiconductor devices with DDR SDRAM face challenges in efficiently controlling data input/output operations and increasing operation speed without requiring additional circuits for changing data order, which affects area and current consumption.
Innovation Solution
A semiconductor device that selectively generates multiple internal clocks from divided clocks and ground voltage based on operation modes to determine data input/output order in synchronization, eliminating the need for separate circuits to change data order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate circuits are added to change data input/output order, then data ordering flexibility is improved, but device area increases
Solution Approach 1:
The internal clock generation circuit is designed to perform multiple functions: it generates clock signals for timing control and simultaneously determines the data input/output order based on different operational modes. This multi-functionality eliminates the need for separate data ordering circuits, resolving the contradiction between data ordering flexibility and device area.
Solution Approach 2:
The patent combines the clock generation function with the data ordering control function into a single integrated circuit. By merging these previously separate functions, the patent achieves data ordering flexibility without requiring additional separate circuits, thus reducing device area while maintaining adaptability.
2Adaptability or versatility
If separate circuits are added to change data input/output order, then data ordering flexibility is improved, but current consumption increases
Solution Approach 1:
The internal clock generation circuit serves dual purposes: timing control and data ordering determination. This multi-functionality allows the circuit to provide data ordering flexibility without requiring additional separate circuits that would consume extra current, thus resolving the contradiction between adaptability and energy usage.
Solution Approach 2:
By combining clock generation and data ordering control into a single circuit, the patent eliminates redundant circuitry that would increase current consumption. The merged circuit achieves both timing control and data ordering flexibility while consuming less power than separate circuits would require.
3Speed
If multiple divided clocks are used to control pipe latch circuit, then operation speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the clock signal into multiple divided clocks with different frequencies, each serving specific pipeline stages. This segmentation allows high-speed operation in critical paths while using lower frequencies in less time-sensitive stages, achieving high operation speed without requiring all circuits to operate at maximum speed, thus reducing overall device complexity.
Solution Approach 2:
The patent implements dynamic clock frequency selection where different pipeline stages operate at different clock frequencies based on their specific requirements. This dynamic approach allows high-speed operation where needed while maintaining simplicity in less demanding stages, resolving the contradiction between operation speed and device complexity.
Data Source
AI summary
A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.