Semiconductor IC Clock Noise Reduction via Opposite Polarity Pads

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Solution Overview

Problem

Conventional FM multiplex broadcast receivers experience significant noise interference due to parasitic capacitances affecting the operating characteristics of low-pass and band-pass filters in semiconductor integrated circuit devices, particularly from single-phase clock signals.

Innovation Solution

The introduction of a second electrode pad receiving a clock signal with the same frequency but opposite polarity, adjacent to the first electrode pad, and isolated from the integrated circuit block, which cancels out noise caused by parasitic capacitances when both clock signals are supplied to the semiconductor integrated circuit device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single-phase clock signal is supplied to the semiconductor integrated circuit device, then the circuit operates normally, but clock noise is generated due to parasitic capacitances affecting filter characteristics

Engineering Contradiction:

Improvecircuit operationVSAvoidclock noise

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies the counterweight principle by introducing a second electrode pad with opposite polarity clock signal to counterbalance the noise generated by the first electrode pad. The parasitic capacitances Cp2 and Cp4 associated with the second electrode pad create noise that is equal in magnitude but opposite in polarity to the noise from the first electrode pad, causing the noise components to cancel each other out and reduce overall clock noise affecting the filter circuits.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

Solution Approach 2:

The patent converts the harmful effect of parasitic capacitances into a beneficial noise cancellation mechanism. By strategically placing the second electrode pad with opposite polarity clock signal, the previously harmful parasitic capacitances Cp2 and Cp4 are transformed into useful elements that generate compensating noise signals, turning the original problem source into a solution mechanism.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Length of stationary object

If electrode pads are placed close to integrated circuit blocks, then wiring length is reduced, but noise coupling through parasitic capacitances increases

Engineering Contradiction:

Improvewiring lengthVSAvoidnoise coupling

Core Design Contradiction:

Length of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent maintains short wiring by placing the second electrode pad adjacent to the first electrode pad near the integrated circuit blocks, and uses the opposite polarity clock signal to create a counterbalancing noise field. This allows the beneficial short wiring configuration to be maintained while the noise coupling issue is resolved through the noise cancellation mechanism between the two electrode pads.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

3Object-affected harmful factors

If multiple electrode pads are added to the semiconductor substrate, then noise cancellation is achieved, but device complexity increases

Engineering Contradiction:

Improveclock noise reductionVSAvoidelectrode pad configuration

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent achieves noise cancellation with minimal added complexity by introducing only one additional electrode pad (the second electrode pad) with opposite polarity clock signal. This simple symmetric configuration provides effective noise reduction without requiring complex multi-pad arrangements or sophisticated noise cancellation circuits, maintaining ease of implementation.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces clock noise, enhancing the sensitivity of FM-signal reception and allowing for more flexible circuit placement, including integration of the FM tuner and analog filter IC into a single IC chip.

Implementation Method 1

parasitic capacitances Cp1, Cp2, Cp3, and Cp4, shown in FIG. 8, between the electrode pad 41 of the IC chip 40 and the integrated circuit blocks 45, 47, 49, and 50 respectively cause noise

Methodology Applied

Scientific EffectParasitic capacitance: Capacitance

Implementation Method 2

a second electrode pad which receives a second clock having the same frequency as and opposite polarity from the first clock, the second electrode pad being disposed in a position adjacent to the first electrode pad on the semiconductor substrate and isolated from the integrated circuit block

Methodology Applied

Scientific EffectNoise cancellation through opposite polarity signals: Electromagnetic Induction

Data Source

PatentUS7307484B2Semiconductor integrated circuit device with noise reduction function

Publication Date: 2007.12.11 LAPIS SEMICON CO LTD

AI summary

A semiconductor integrated circuit device includes a semiconductor substrate; at least one integrated circuit block formed in the semiconductor substrate; a first electrode pad which receives a first clock, the first electrode pad being disposed on the semiconductor substrate; a wiring line which electrically connects the integrated circuit block and the first electrode pad, the wiring line being disposed on the semiconductor substrate; and a second electrode pad which receives a second clock having the same frequency as and opposite polarity from the first clock, the second electrode pad being disposed in a position adjacent to the first electrode pad on the semiconductor substrate and isolated from the integrated circuit block.