Semiconductor Clock Self-Training for Internal Phase Synchronization
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Solution Overview
Problem
Existing semiconductor data processing systems require additional hardware and software resources for phase training operations, leading to increased workload and reduced accuracy due to asynchronous phase adjustments and reliance on Error Detection Code (EDC) for result transfer.
Innovation Solution
A semiconductor apparatus with a self-training circuit that performs internal phase training by dividing clock signals to generate multi-phase signals, detecting phase differences, and adjusting phases without external controller intervention, reducing the workload and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller performs phase training operations using delay lines and EDC pins, then phase synchronization between clock signals is achieved, but additional hardware and software resources are required, increasing device complexity and workload
Solution Approach 1:
The semiconductor apparatus performs phase training operations autonomously using its own internal circuits (dividing circuit, phase detecting circuitry, phase control circuit, phase adjusting circuit) without requiring external controller intervention. The apparatus detects phase differences between clock signals and adjusts its internal phases self-service, eliminating the need for controller delay lines and EDC pin communications.
Solution Approach 2:
The phase training functionality is extracted from the controller and relocated to the semiconductor apparatus. By removing the training operation requirements from the controller side, the patent eliminates the need for controller delay lines, EDC pin communications, and associated software, thereby reducing controller device complexity while maintaining phase synchronization reliability.
2Ease of operation
If phase training is performed asynchronously with EDC result transfer, then phase adjustment can be made, but the workload on the controller increases and accuracy is reduced
Solution Approach 1:
The semiconductor apparatus autonomously performs phase detection and adjustment operations without requiring controller intervention. The internal phase detecting circuitry continuously monitors phase differences and the phase control circuit automatically adjusts clock signal phases, eliminating asynchronous EDC result transfers and reducing controller workload while improving training accuracy through continuous internal optimization.
Solution Approach 2:
The phase training operation transitions from asynchronous discrete adjustments to continuous internal optimization. The semiconductor apparatus continuously monitors phase differences and makes real-time adjustments without interruption or external coordination, eliminating the gaps and coordination overhead inherent in asynchronous EDC-based training, thereby improving both productivity and accuracy.
3Extent of automation
If the semiconductor apparatus uses internal dividing circuits to generate multi-phase signals, then phase training can be performed internally, but additional internal circuits are required
Solution Approach 1:
The phase training function is segmented into dedicated internal modules: dividing circuit for generating multi-phase signals, phase detecting circuitry for measuring phase differences, phase control circuit for generating control signals, and phase adjusting circuit for correcting phases. This segmentation enables automated internal training while organizing complexity into manageable, specialized functional blocks that work together efficiently.
Data Source
AI summary
A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.