Semiconductor Device Clock Wiring Area Reduction
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Solution Overview
Problem
As the number of memory devices increases in a semiconductor device, the lengthening of clock signal wiring to equalize delays with command and address signal wiring leads to increased occupied area and potential delays that may not satisfy JEDEC specifications, affecting memory read operations.
Innovation Solution
The semiconductor device employs a configuration where two pairs of memory devices are commonly coupled to differential clock terminals, allowing for earlier output timing of command and address signals relative to clock signals, reducing the need for longer clock wiring and minimizing load capacitance, thereby maintaining synchronization without increasing clock wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the clock signal wiring is separately provided for each memory device to prevent waveform distortion, then the clock signal quality is improved, but the occupied area of the clock wiring on the wiring substrate increases and the number of clock terminals increases
Solution Approach 1:
The patent combines multiple memory devices (specifically two pairs of memory devices) to share common clock terminals. This merging approach reduces the total number of clock terminals needed from four (one per memory device) to two (shared by pairs), thereby reducing the occupied area of clock wiring on the wiring substrate while maintaining proper clock signal distribution to all memory devices
2Manufacturing precision
If the clock signal wiring is lengthened to equalize delays with command and address signal wiring, then the delay equalization is improved, but the occupied area of the clock wiring increases and the round trip time increases
Solution Approach 1:
The patent applies preliminary action by adjusting the output timing of the command and address signal to occur earlier than the clock signal. This timing adjustment compensates for the inherent delay differences without requiring physical lengthening of the clock wiring, thereby achieving delay equalization while minimizing the occupied area of clock wiring
3Device complexity
If each two memory devices are commonly coupled to each of two pairs of differential clock terminals, then the number of clock terminals is reduced, but the load capacitance increases
Solution Approach 1:
The patent applies parameter changes by carefully designing the clock signal distribution network to accommodate the increased load capacitance from multiple memory devices sharing common clock terminals. This involves adjusting wiring characteristics and signal timing parameters to ensure proper signal integrity despite the increased capacitive load
4Manufacturing precision
If the clock wiring is lengthened to equalize delays, then the delay equalization is improved, but the wiring delay increases and the round trip time increases
Solution Approach 1:
The patent uses preliminary action by advancing the output timing of the command and address signal relative to the clock signal. This timing adjustment pre-compensates for transmission delays, allowing delay equalization to be achieved without physically lengthening the clock wiring, thereby avoiding increased round trip time
Data Source
AI summary
Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.