Semiconductor Metallization Coating to Prevent Cavities and Oxidation
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Solution Overview
Problem
Existing semiconductor substrate arrangements often experience yield loss due to unwanted cavities and trenches in the metallization layers, which can harbor contaminants and lead to oxidation issues during sintering and subsequent processes.
Innovation Solution
A semiconductor substrate arrangement is designed with a dielectric insulation layer and a first metallization layer, where an electrically conductive coating is applied vertically over the metallization layer, ensuring that the metallization layer is free from cavities or trenches within a specific distance from the coating's perimeter, thereby minimizing contaminant retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thin metallic coating is arranged between the metallic connection layer and the first metallization layer, then mechanical and electrical coupling is improved, but unwanted cavities and trenches form in the first metallization layer
Solution Approach 1:
The patent changes the physical and chemical parameters of the metallization layer by adding an intermediate layer with specific material properties (different from both the metallic coating and the base metallization layer). This intermediate layer has controlled thickness, composition, and structural characteristics that enable it to bridge the interface between the metallic coating and the first metallization layer, reducing stress concentration and preventing cavity formation during the deposition process.
Solution Approach 2:
The patent introduces an intermediate layer as a mediator between the metallic coating and the first metallization layer. This intermediate layer serves as a transition zone that facilitates gradual adaptation of material properties, reduces thermal and mechanical stress gradients, and prevents direct interface defects. The intermediate layer acts as a buffer that maintains integrity of both interfaces while enabling strong mechanical and electrical coupling.
2Reliability
If the metallic coating is formed on the semiconductor substrate, then electrical conductivity is improved, but contaminants remain in the cavities causing oxidation during sintering
Solution Approach 1:
The intermediate layer serves as a protective mediator that prevents contaminants from being trapped in cavities at the interface between the metallic coating and the first metallization layer. By providing a gradual transition and eliminating sharp interfaces, the intermediate layer reduces cavity formation where contaminants could be trapped. Additionally, the intermediate layer itself can act as a barrier to oxidation during subsequent sintering processes.
Solution Approach 2:
The patent converts the potentially harmful effect of interface stresses and cavity formation into a benefit by deliberately designing an intermediate layer that absorbs these stresses. The intermediate layer's controlled properties allow it to accommodate thermal and mechanical expansions, transforming what would be defect-generating stress concentrations into a protective stress-dissipating structure that prevents contaminant trapping and oxidation.
3Ease of manufacture
If conventional metallization layer formation is used, then manufacturing simplicity is maintained, but yield loss occurs due to oxidation at the end of line
Solution Approach 1:
The patent applies preliminary action by incorporating the intermediate layer during the initial metallization layer formation process, before subsequent contamination and oxidation risks arise. This intermediate layer is deposited as part of the base structure, pre-establishing a protective and stress-managing interface that prevents future defects. The preliminary inclusion of this layer ensures that cavities and contamination pathways are prevented before they can compromise yield in later sintering and assembly steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the risk of yield loss by preventing the formation of large cavities and trenches, which can harbor contaminants and cause oxidation issues, thereby enhancing the reliability and longevity of the semiconductor substrate.
Implementation Method 1
When forming the metallic coating on the semiconductor substrate, usually unwanted cavities occur in the first metallization layer in direct proximity to the metallic coating
Data Source
AI summary
A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.