Semiconductor Apparatus Code Area Segmentation

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Solution Overview

Problem

Conventional semiconductor apparatuses face limitations in efficiently processing and storing large amounts of data with low power consumption, especially in mobile devices with limited physical space, due to the need for high-performance computing and memory integration.

Innovation Solution

A semiconductor apparatus with a storage device having a data area and a code area, integrated with multiple unit processors and a main control component that receives and executes operation policies including processor IDs, code IDs, and code addresses to manage and allocate program codes across processors, allowing for efficient data processing and storage without separate RAM or ROM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If program codes are stored in separate RAM or ROM, then program codes can be executed, but device complexity increases and power consumption increases

Engineering Contradiction:
Improvedevice complexityVSAvoidprogram code execution capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent merges the storage of program codes with the data storage function by implementing a code area within the storage device. This eliminates the need for separate ROM or RAM components, reducing device complexity while maintaining program code execution capability through the integrated storage structure.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If multiple program codes are stored and executed within the apparatus, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvedata processing speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the storage device into distinct code area and data area, allowing multiple program codes to be stored and executed simultaneously without interfering with data storage operations. This segmentation enables parallel processing and improves productivity while managing complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The storage device is designed with multi-functionality, serving both as data storage and program code storage/execution. The code area allows the same storage apparatus to execute multiple program codes, enhancing productivity without requiring separate dedicated code storage hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If program codes are updated frequently, then adaptability improves, but loss of time increases due to frequent rebooting

Engineering Contradiction:
Improveprogram code update capabilityVSAvoidreboot time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements a code area where program codes are pre-stored in the storage device before execution is needed. When program codes need to be updated or executed, the system can directly access the code area without requiring system reboots, as the codes are already prepared in the storage medium. This eliminates time loss associated with frequent rebooting while maintaining adaptability for code updates.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11068283B2Semiconductor apparatus, operation method thereof, and stacked memory apparatus having the same
Publication Date: 2021.07.20 SK HYNIX INC
  • US11068283B2 patent drawing
  • US11068283B2 patent drawing
  • US11068283B2 patent drawing

AI summary

A semiconductor apparatus may include a storage device including a data area and a code area and storing program codes provided from a host device in the code area, a plurality of unit processors, each of the plurality of unit processors including an internal memory, and a main control component configured to receive an operation policy, which includes a processor ID, a code ID, and a code address, from the host device and to control the plurality of unit processors based on the operation policy. The processor ID is an identifier for each of the plurality of unit processors, the code ID is an identifier for each of the program codes, and the code address indicates a position of the code area where each of the program codes is stored.