Semiconductor Column Control Circuit Error Correction
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Solution Overview
Problem
The increasing number of failed memory cells in semiconductor devices due to advanced fabrication techniques leads to reduced production yield and difficulty in ensuring large memory capacity, necessitating effective error correction mechanisms.
Innovation Solution
A semiconductor system comprising a first semiconductor device outputting command/address signals and a second semiconductor device that extracts error information during a read operation, corrects errors, and stores the corrected data and error information during a refresh operation, replacing faulty addresses with new ones to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced fabrication process techniques are used to increase integration, then device functionality and capacity are improved, but the number of failed memory cells increases
Solution Approach 1:
The patent performs preliminary identification of failed memory cells during a first refresh operation by detecting data errors, storing error information including failed cell addresses, and preparing correction mappings before normal operations. This preliminary action enables subsequent correction operations to efficiently address errors without disrupting normal memory functionality.
Solution Approach 2:
The patent creates a copy of error information from the first refresh operation and uses it to guide correction operations in subsequent refresh operations. The error information including failed cell addresses and corresponding good cell addresses is stored and reused to systematically correct errors across multiple operations.
2Reliability
If failed memory cells are identified and corrected, then data reliability is improved, but additional refresh operations are required
Solution Approach 1:
The patent merges the error correction function with the existing refresh operation framework. Instead of adding separate correction operations that would increase time loss, the correction functionality is integrated into the refresh operation sequence, allowing errors to be corrected during scheduled refresh cycles without adding extra time overhead.
Solution Approach 2:
The patent maintains continuous correction capability across multiple refresh operations. By storing error information and applying corrections systematically in each refresh cycle, the useful action of error correction continues without interruption, progressively improving data reliability while utilizing the existing refresh operation timing.
3Reliability
If error correction code circuits are employed, then data errors are corrected, but device complexity increases
Solution Approach 1:
The patent implements a self-service error correction mechanism where the memory system automatically identifies failed cells, generates error information, creates correction mappings, and applies corrections without external intervention. The system uses its own refresh operations and internal resources to perform correction, avoiding the need for complex external ECC circuitry.
Solution Approach 2:
The patent changes the operational parameters of existing memory cells to enable correction functionality. By utilizing the same memory cells as both data storage and error information storage, and by changing the state of cells from simple data holders to active participants in the correction process, the system achieves error correction without adding complex dedicated correction circuits.
Data Source
AI summary
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command/address signals. The second semiconductor device may be configured to output data in a read operation during a refresh operation according to a combination of the command/address signals. The second semiconductor device may be configured to extract error information from the data. The second semiconductor device may be configured to corrects errors of the data using the error information in a write operation during the refresh operation to store the corrected data in the second semiconductor device and to store the error information in the second semiconductor device.