Semiconductor Column Control Circuit Masked Write Signal Segmentation
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Solution Overview
Problem
Semiconductor devices face challenges in performing masked write operations efficiently, particularly in managing internal read and write operations concurrently without signal collision, which affects the reliability of data transfer.
Innovation Solution
The semiconductor device incorporates a column control circuit and core circuit configuration that generates read and write column signals based on bank address signals and latch pulses, allowing for sequential activation of banks to perform internal read and write operations, thereby preventing signal collisions and enhancing operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent internal read and write operations are performed during masked write operation, then productivity is improved, but signal collision occurs reducing reliability
Solution Approach 1:
The patent segments the column signal generation into separate paths for read operations and write operations. The read column signal is generated based on read bank address signals and read latch pulses, while the write column signal is generated based on write bank address signals and write latch pulses. This segmentation prevents signal collision by ensuring that read and write operations use distinct signal generation pathways, thereby maintaining reliability while allowing concurrent operations to improve productivity.
2Reliability
If separate signal generation for read and write operations is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the read column signal generation circuit and write column signal generation circuit into a unified column control circuit. Both read and write column signals are generated within the same circuit block using similar structural elements (bank address signals, latch pulses, and signal generation logic), but with separate signal pathways. This merging approach maintains reliability through separate signal paths while reducing device complexity by avoiding complete duplication of independent circuits.
Data Source
AI summary
A semiconductor device includes a column control circuit and a core circuit. The column control circuit generates a read column signal and a write column signal from a read bank address signal and a write bank address signal in response to a read latch pulse and a write latch pulse, which are generated during a masked write operation. The core circuit is configured to include a plurality of banks. Any one of the plurality of banks is activated by the read column signal and the write column signal to perform an internal read operation and a write operation.