Semiconductor Column Decoder Segmentation for Signal Path Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing height of memory cell banks in semiconductor devices lengthens signal transmission paths, leading to increased column-to-column delay and degraded performance due to the need for higher memory cell density.
Innovation Solution
A semiconductor device design that includes a first and second column decoder arranged on opposite sides of the bank, with a column decoder selection circuit activating either decoder based on the row address, allowing for reduced signal transmission paths by using different decoders for upper and lower regions of the bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the bank is increased to increase memory cell density, then the memory cell integration density is improved, but the signal transmission path length is lengthened causing increased column-to-column delay
Solution Approach 1:
The column decoder is divided into two separate decoders (first column decoder and second column decoder) positioned at opposite sides of the bank. This segmentation allows the bank to be accessed from both ends, effectively halving the average signal transmission path length while maintaining high memory cell density in the vertically extended bank structure.
Solution Approach 2:
The patent introduces a dual-sided access architecture where column decoders are placed at both the top and bottom (or opposite sides) of the bank, transforming the single-directional signal transmission into a two-directional system. This dimensional change in signal access path enables shorter transmission distances without compromising the vertical stacking of memory cells for high density.
2Device complexity
If a single column decoder is used for the entire bank, then the device complexity is reduced, but the column-to-column delay increases due to longer transmission paths
Solution Approach 1:
The column decoder functionality is segmented into two separate decoder units positioned at opposite sides of the bank. Each decoder handles column selection for its respective side, reducing the maximum transmission distance for column select signals and thereby decreasing column-to-column delay, with the added complexity being justified by the performance improvement.
Solution Approach 2:
A column decoder selection circuit acts as an intermediary that selectively activates either the first or second column decoder based on the row address. This mediator coordinates between the two decoders and the control logic, enabling the system to switch between decoders to optimize signal path length while managing the overall device complexity.
Data Source
AI summary
A semiconductor device may include a first column decoder arranged at a first side of a bank, wherein the first column decoder is enabled by a first column decoder select signal. The semiconductor device may include a second column decoder arranged at a second side of the bank, wherein the second column decoder is enabled by a second column decoder select signal; and wherein the bank is arranged between the first column decoder and the second column decoder. The semiconductor device may further include a column decoder selection circuit suitable for activating any one of the first and second column decoder select signals based on a row address.