Semiconductor Column Selection Line Defect Detection Circuit
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Solution Overview
Problem
Current semiconductor devices cannot effectively distinguish between defects in column selection lines and bit lines during manufacturing tests, leading to unnecessary chip discard and wasteful packaging costs, as defects in column selection lines cause all connected bit lines to become defective, making it difficult to identify and address the issue before packaging.
Innovation Solution
A semiconductor device with a comparison circuit that generates multiple comparison results and determining circuits to differentiate between bit line and column selection line defects by evaluating read data from memory cells, allowing for the detection of column selection line defects before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a comparison result is compressed into a one-bit compressed determination signal to shorten testing time, then testing time is reduced, but the ability to distinguish between column selection line defects and bit line defects is lost
Solution Approach 1:
The patent segments the compressed determination signal into multiple determination signals (first determination signal for bit line defects, second determination signal for column selection line defects). This segmentation allows the system to maintain quick testing while precisely identifying the type of defect, resolving the contradiction between testing speed and defect detection precision.
2Device complexity
If all comparison results are compressed into one determination signal, then device complexity is reduced, but the ability to identify column selection line defects is lost
Solution Approach 1:
The determination circuit is segmented into multiple independent determination circuits, each responsible for a specific defect type. This segmentation enables precise defect identification without significantly increasing overall device complexity, as each circuit handles a specific function.
Solution Approach 2:
The patent uses preliminary action by setting up the determination circuits to evaluate comparison results in a structured manner before final defect classification. The first determination circuit checks for any mismatches, and the second determination circuit specifically checks for all-mismatch conditions, enabling systematic defect identification.
3Productivity
If chips with potential defects are packaged without detection, then packaging throughput is maintained, but defective chips are shipped causing customer issues
Solution Approach 1:
The patent performs preliminary defect detection during wafer-state testing before packaging. By identifying column selection line defects and bit line defects early, the system ensures that only truly functional chips are packaged, maintaining both productivity and reliability.
Solution Approach 2:
The determination circuits provide feedback signals that indicate the type of defect detected. This feedback mechanism allows the testing system to quickly identify and flag defective chips, enabling efficient sorting and ensuring that only good chips proceed to packaging.
Data Source
AI summary
To include a comparison circuit that generates comparison results by comparing plural pieces of data simultaneously read via data lines with expected values, an AND gate that activates a first determination signal in response to a fact that at least one of the comparison results indicates a mismatch, and an OR gate that activates a second determination signal in response to a fact that all the comparison results indicate a mismatch. With this arrangement, when a detection test of a defective address is performed in a wafer state, a defect of a column selection line can be detected.