Semiconductor Column Line Selection Circuit for Memory Repair
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Solution Overview
Problem
Current semiconductor devices face inefficiencies in performing repair operations due to the lack of an effective method for simultaneously managing redundancy and normal fuse data for column line repairs, which complicates the identification and correction of fail cells across memory blocks.
Innovation Solution
The semiconductor device incorporates a column line selection circuit that uses redundancy and normal fuse data to simultaneously perform repair operations across memory blocks, generating test column addresses to select and output data from column lines, and an input/output control circuit to process this data, thereby reducing the complexity of fail cell identification and repair verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repair operations are performed separately for each memory block, then the repair process is simple to manage, but the total repair time increases and productivity decreases
Solution Approach 1:
The patent merges the repair operations of multiple memory blocks by simultaneously activating repair operations across first and second memory blocks using a unified repair control mechanism. This allows redundant column lines to be effectively utilized across multiple blocks, improving repair productivity while managing complexity through integrated control
2Reliability
If test operations are performed on all column lines, then fail cell detection is thorough, but the test time increases significantly
Solution Approach 1:
The patent performs preliminary testing by generating test column addresses that target only column lines requiring verification. By predicting which column lines need testing based on redundancy activation patterns, the system conducts pre-test operations on selected column lines before actual repair, reducing overall test time while maintaining detection reliability
Solution Approach 2:
Instead of testing all column lines exhaustively, the patent applies partial action by limiting test operations to only those column lines that are candidates for repair or have been activated as redundant. This selective approach reduces test time while maintaining sufficient reliability for fail cell detection
3Productivity
If multiple column lines are selected for repair simultaneously, then repair productivity increases, but the complexity of managing fuse data increases
Solution Approach 1:
The patent implements universality by creating a unified repair control mechanism that manages both normal and redundant fuse data across multiple memory blocks through a single control interface. This allows simultaneous repair operations on multiple column lines while presenting a simplified management interface, effectively handling multi-functionality in fuse data management
Data Source
AI summary
A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.