Semiconductor Column Selection Signal Delay Control
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Solution Overview
Problem
Semiconductor devices, such as DRAM, face challenges in efficiently managing column selection signals for memory operations due to identical address allocation across memory banks, leading to power consumption issues and inefficiencies in data transmission.
Innovation Solution
A semiconductor device incorporating a section signal generator that retards a pre-section signal by a delay time set according to test mode signal levels, combined with a decoder to generate column selection signals, enables selective data storage or output, and includes a multiplexer to output delay signals based on selection signals, optimizing power consumption by activating only necessary delay units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay units are activated for all memory banks to ensure simultaneous data output, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by enabling delay units selectively based on memory bank activity. Specifically, the column path circuit activates delay units only for memory banks that are currently undergoing read or write operations, while keeping delay units inactive for idle memory banks. This localized activation ensures that data transmission reliability is maintained for active banks without incurring unnecessary power consumption from activating delay units for all banks simultaneously.
2Productivity
If multiple delay units are activated to handle simultaneous operations in multiple memory banks, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamics by making the activation state of delay units changeable based on real-time memory bank activity. The column path circuit dynamically determines which delay units to activate according to the current operational status of each memory bank, allowing the system to adapt its complexity level to the actual workload. This dynamic approach enables efficient handling of simultaneous operations when needed while reducing complexity during periods of lower activity.
3Reliability
If delay time is increased to synchronize data output from different memory banks, then data transmission reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies parameter changes by adjusting the delay time parameter dynamically based on memory bank activity status. The column path circuit modifies the delay time applied to section signals according to whether memory banks are currently active or idle. This selective parameter adjustment ensures that delay is applied only when necessary for synchronization, maintaining data transmission reliability while minimizing unnecessary time delays that would occur if a fixed delay was applied to all operations.
Data Source
AI summary
A semiconductor device includes a section signal generator and a decoder. The section signal generator generates a section signal by retarding a pre-section signal including a pulse created during a read operation or a write operation by a delay time that is set according to a level combination of first and second test mode signals. The decoder decodes address signals in response to a pulse of the section signal to generate column selection signals, one of which is selectively enabled, to store an external data in a memory cell of an internal circuit or to output a data stored in a memory cell of an internal circuit.