Semiconductor Device Integrating Columnless and Super-Junction Power MOS Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with power MOS transistors face challenges in reducing on resistance and preventing backflow current, especially when used in vehicle-mounted applications where reverse coupling of battery cables can occur, leading to increased current flow through parasitic diodes.
Innovation Solution
The semiconductor device incorporates a combination of power MOS transistors with a columnless structure and a super-junction structure, where the first transistor prevents backflow by having a lower withstand voltage and the second transistor handles normal operations with a higher withstand voltage, both formed on the same semiconductor substrate to reduce on resistance and prevent current flow in reverse coupling scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two power MOS transistors with identical properties are used to prevent backflow current, then backflow prevention is achieved, but on resistance substantially doubles
Solution Approach 1:
The patent applies local quality by assigning different characteristics to different parts of the system: the first power MOS transistor has a lower withstand voltage optimized for backflow prevention, while the second power MOS transistor has a higher withstand voltage optimized for normal operation. This local differentiation allows each transistor to be optimized for its specific function, preventing the need for both transistors to have identical high-withstand-voltage characteristics that would double the on resistance.
Solution Approach 2:
The patent changes the parameter of withstand voltage between the two power MOS transistors. The first transistor is designed with a withstand voltage lower than the battery voltage (optimized for backflow prevention), while the second transistor has a withstand voltage higher than the battery voltage (optimized for normal operation). This parameter differentiation resolves the contradiction by allowing the first transistor to have lower on resistance while still preventing backflow.
2Reliability
If two power MOS transistors are coupled in series to prevent backflow, then backflow is prevented, but device complexity increases
Solution Approach 1:
The patent merges two power MOS transistors with different characteristics into a single integrated circuit device. By combining the first power MOS transistor (for backflow prevention) and the second power MOS transistor (for normal operation) into one device with a shared drain region, the patent reduces overall system complexity compared to using two separate devices, while maintaining the series configuration needed for backflow prevention.
Solution Approach 2:
The integrated circuit device achieves multi-functionality by incorporating two power MOS transistors with different withstand voltages into a single device. The first transistor handles backflow prevention while the second transistor handles normal operation, allowing one device to perform multiple functions that would otherwise require separate components, thereby reducing overall system complexity.
3Reliability
If two separate semiconductor substrates are used for the power MOS transistors, then each transistor can be optimized independently, but manufacturing cost and device size increase
Solution Approach 1:
The patent merges two power MOS transistors that would traditionally require separate semiconductor substrates into a single integrated circuit device. By sharing a common semiconductor substrate and drain region, the patent reduces the quantity of substrate material needed while maintaining the ability to independently optimize each transistor's characteristics through different region configurations on the same substrate.
Solution Approach 2:
The patent implements a nested structure where the first power MOS transistor and second power MOS transistor are integrated within a single semiconductor substrate. The transistors share common regions (drain region, epitaxial layer, substrate) while maintaining distinct source and gate regions, creating a nested configuration that reduces material usage compared to two separate devices.
Data Source
AI summary
A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.