Semiconductor Combination Rows for Compact HP/LP Cell Layouts
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Solution Overview
Problem
Existing semiconductor device design rules struggle to efficiently optimize the placement and spacing of conductive patterns in metallization levels, particularly in integrating high power (HP) and low power (LP) cells, leading to suboptimal layout diagrams that consume more area than necessary.
Innovation Solution
The method involves arranging cells in rows with combination rows that stack HP cells over LP cells or vice versa, setting specific pitches for different metallization levels, and configuring the height of rows to accommodate both cell types, allowing for more efficient placement and area reduction by using a combination of sole-pitch and multi-pitch configurations for conductive patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional design rules are used for placing conductive patterns in metallization levels, then manufacturing reliability is maintained, but layout area efficiency deteriorates due to excessive spacing requirements between HP and LP cells
Solution Approach 1:
The patent segments the layout into distinct row types (HP-only rows, LP-only rows, and combination rows) with specific pitch configurations. Each row type is optimized for its intended cell type, allowing HP cells and LP cells to be placed in rows with appropriate spacing requirements, thereby reducing overall layout area while maintaining manufacturing reliability through dedicated pitch settings for each cell type.
Solution Approach 2:
The patent applies different pitch settings locally to different metallization levels and row types. Specifically, M1 and M2 metallization levels have different pitch values (PM1 and PM2 respectively), and combination rows have specialized pitch configurations that differ from standard HP-only or LP-only rows. This local differentiation allows optimized spacing for each cell type while maintaining overall design reliability.
2Adaptability or versatility
If uniform pitch settings are applied across all metallization levels, then manufacturing process simplicity is maintained, but layout optimization capability deteriorates due to inability to accommodate different cell spacing requirements
Solution Approach 1:
The patent divides the metallization structure into segments with different pitch characteristics. M1 metallization level uses pitch PM1 while M2 metallization level uses pitch PM2, where PM1 ≠ PM2. This segmentation allows each metallization level to be optimized for specific cell types and spacing requirements, enhancing layout optimization capability while managing complexity through systematic pitch assignment.
Solution Approach 2:
The patent creates a universal pitch configuration system that can accommodate both HP cells and LP cells through different row types. The combination rows, in particular, serve multiple functions by supporting both HP and LP cell placements with appropriate pitch settings, making the design adaptable to various cell combinations without requiring completely separate design rules for each cell type.
3Area of stationary object
If HP cells and LP cells are placed in separate dedicated rows, then manufacturing reliability is improved through consistent spacing, but layout area efficiency deteriorates due to increased total row count
Solution Approach 1:
The patent merges HP cell rows and LP cell rows into combination rows where HP cells and LP cells coexist in the same physical row structure. This merging allows efficient utilization of vertical space by stacking cells of different types in alternating patterns within the same row, significantly reducing the total layout area while maintaining manufacturing precision through dedicated pitch settings that ensure proper spacing between adjacent cells regardless of type.
Solution Approach 2:
The patent introduces dynamic pitch selection based on the specific cell type and position within a row. Combination rows can switch between different pitch configurations (PM1 for M1 level, PM2 for M2 level) depending on whether an HP cell or LP cell is being placed at a given location. This dynamic adaptation allows precise control over cell spacing to maintain manufacturing precision while achieving compact layout arrangement.
Data Source
AI summary
A semiconductor device includes cell regions in rows, each row including at least one instance of a first or second cell region, each of the first and second cell regions including: structures in a transistor layer; conductive segments in an M_1st layer and extending substantially in a first direction (row direction), the M_1st layer having a first pitch as a sole pitch for the conductive segments of the M_1st layer; conductive segments in an M_2nd layer; and conductive segments in an M_3rd layer, including conductive segments for a power grid (PG segments) and conductive segments for control or data signals (logic segments), the M_3rd layer having a second pitch for the logic segments and a third pitch for the PG segments, the third pitch being greater than the second pitch, and the second pitch being different from the first pitch.