Semiconductor Device Command Queue Parallel Channel Architecture
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Solution Overview
Problem
The existing semiconductor devices face challenges in transferring data between a host and memory chips at high speeds due to the limited bandwidth of the wired communication path and the slow communication speed between the bridge chip and individual chips, leading to waiting times when processing commands.
Innovation Solution
A semiconductor device is designed with a command queue that stores multiple read commands and a read buffer memory to buffer read data, allowing for parallel execution of commands across multiple channels, thereby improving data transfer speed by sequentially issuing commands and storing read data based on execution status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If commands are processed sequentially through a single channel, then the device complexity is reduced, but the data transfer speed decreases due to waiting times
Solution Approach 1:
The semiconductor device is divided into multiple channels (first channel and second channel), each capable of independently processing commands. This segmentation allows parallel command execution across channels, improving data transfer speed while distributing the processing load to manage complexity
Solution Approach 2:
The patent introduces a time dimension by implementing a command queue that stores multiple read commands for sequential execution. This allows the system to pipeline commands across different channels and time periods, effectively increasing throughput without proportionally increasing simultaneous channel count
2Productivity
If the bandwidth of individual channels is limited, then the device complexity remains low, but the productivity decreases due to bottlenecked data transfer
Solution Approach 1:
Multiple channels are merged into a unified command processing system with a shared command queue and buffer memory. This allows the aggregate bandwidth of multiple channels to be utilized simultaneously, increasing overall productivity while maintaining individual channel simplicity
Solution Approach 2:
Read commands are stored in advance in a command queue before execution. This preliminary action allows the system to prepare and stage multiple commands, enabling continuous command issuance to different channels and improving productivity by eliminating idle waiting time
3Speed
If multiple read commands are executed in parallel across multiple channels, then the data transfer speed improves, but the device complexity increases due to command coordination
Solution Approach 1:
A bridge chip is introduced as an intermediary component that manages command distribution across multiple channels. The bridge chip coordinates command execution, handles data buffering, and manages channel allocation, enabling parallel processing while centralizing control logic to manage complexity
Solution Approach 2:
Each channel is designed to be self-sufficient with its own command execution capability and data path. Channels can independently process assigned commands without requiring constant coordination, reducing the complexity of inter-channel communication while maintaining parallel processing efficiency
4Productivity
If waiting times occur during command processing, then the device complexity is reduced, but the productivity decreases due to idle periods
Solution Approach 1:
The command queue and buffer memory enable continuous command issuance and data transfer operations. By pipelining commands across multiple channels and maintaining ready queues, the system eliminates idle periods and ensures continuous productive action, improving overall productivity
Data Source
AI summary
According to one embodiment, there is provided a semiconductor device including a first chip, a second chip group having a plurality of second chips electrically connected to the first chip, and a third chip group having a plurality of third chips electrically connected to the first chip in parallel with the second chip group, in which the first chip has a command queue that stores a plurality of read commands received from the host, and a read buffer memory that buffers read data, sequentially issues the plurality of read commands stored in the command queue to the second chip group or the third chip group, stores the read data corresponding to the plurality of read commands from the second chip group or the third chip group, in the read buffer memory, and transmits any read data among the read data stored in the read buffer memory to the host based on an execution status of any read command among the plurality of read commands.