Semiconductor Device Common Capacitor Electrode Layer
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Solution Overview
Problem
In prior art semiconductor devices, the construction of logic-circuit and memory formation sections interfere with each other, leading to inefficient manufacturing and potential defects, such as high aspect ratios in logic-circuit contact structures that can result in reduced yield and operation speed, and increased power consumption due to shorter DRAM refresh time.
Innovation Solution
A semiconductor device with a multi-layered insulating structure where capacitors in the memory formation section have a common capacitor electrode layer that is lattice-like and regularly arranged, allowing for efficient electrical connection and reducing the aspect ratio of logic-circuit contact structures, while also forming conductive structures and connection layers to maintain electrical connectivity without increasing capacitor height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the logic-circuit formation section and memory formation section are simultaneously constructed using conventional processes, then both sections can be formed in the same semiconductor substrate, but the constructions interfere with each other leading to reduced manufacturing efficiency and potential defects
Solution Approach 1:
The patent segments the semiconductor device into distinct logic-circuit formation section and memory formation section with different structural configurations. The logic-circuit section uses conventional contact structures while the memory section uses capacitors with extended electrode layers, allowing each section to be optimized independently without mutual interference during construction
Solution Approach 2:
The patent applies local quality by giving different structural characteristics to different sections of the semiconductor device. The memory formation section features capacitors with extended upper electrode layers that reach the upper surface of the insulating layer, while the logic-circuit section maintains conventional contact structures, allowing each region to have the optimal structure for its specific function
2Reliability
If the aspect ratio of logic-circuit contact structures is reduced to improve yield and operation speed, then manufacturing efficiency improves, but maintaining electrical connectivity becomes more challenging
Solution Approach 1:
The patent resolves the connectivity challenge by extending the upper electrode layer of the capacitor in the horizontal dimension along the upper surface of the insulating layer. This dimensional extension provides multiple connection points and alternative pathways for electrical connectivity, maintaining ease of operation while allowing the contact structures to have lower aspect ratios for improved reliability
3Quantity of substance
If the height of capacitors is increased to maintain capacitor performance, then electrical capacity improves, but power consumption increases due to shorter DRAM refresh time
Solution Approach 1:
The patent shifts the capacitor design from vertical height increase to horizontal extension. The upper electrode layer extends along the upper surface of the insulating layer, increasing the effective capacitor area and capacity without increasing height. This maintains or improves capacitor performance while avoiding the increased power consumption associated with taller capacitors that have shorter refresh times
Data Source
AI summary
In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section. A signal-line layer is formed in the insulating layer on or above the conductive structure at the logic-circuit formation section so as to be electrically connected to the conductive structure. An upper-side connection layer are formed in the insulating layer at the memory formation section on or above the capacitors so as to be electrically connected to the upper capacitor electrodes.