Semiconductor Device Common Source Line Floating Verify Phase
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing power consumption during program operations due to increased average or peak currents flowing through the common source line during verify phases, which affects efficiency and performance.
Innovation Solution
The semiconductor device and method involve allowing the common source line to float during certain periods of the verify phase, rather than maintaining it at a ground voltage, to prevent or mitigate the increase in current, and applying a first voltage higher than ground to the floating common source line during program phases, thereby optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the common source line is maintained at ground voltage during the verify phase, then the memory cells can be properly evaluated, but the average or peak current through the common source line increases, leading to higher power consumption
Solution Approach 1:
The common source line voltage is made dynamic rather than static. During the verify phase, the voltage on the common source line is allowed to float (become undefined) rather than being fixed at ground voltage. This dynamic approach prevents excessive current flow while still enabling proper memory cell evaluation, thereby reducing power consumption without sacrificing verify operation reliability.
2Use of energy by moving object
If the common source line is allowed to float during the verify phase, then power consumption is reduced, but the current control becomes less predictable
Solution Approach 1:
The control circuit monitors the voltage on the common source line and provides feedback control. When the common source line voltage approaches a threshold level during floating, the control circuit actively adjusts the word line voltage or disables further programming to prevent excessive current. This feedback mechanism ensures that even though the common source line floats during verify phase, the current remains under control and predictable.
3Productivity
If a high voltage is applied to the floating common source line during program phase, then programming efficiency is improved, but the voltage control complexity increases
Solution Approach 1:
The control circuit is pre-programmed with voltage application sequences. Before the program phase begins, the control circuit prepares and applies the appropriate high voltage to the floating common source line in a controlled manner. This preliminary preparation ensures that when programming occurs, the voltage is already optimized for efficient programming, while the control sequence remains manageable and predictable through pre-planned voltage transitions.
Data Source
AI summary
Provided herein is a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on a memory cell selected from among the plurality of memory cells. The control logic is configured to control the peripheral circuit to allow a common source line coupled to the memory block to float in a sensing phase included in a verify phase of the program operation, and thereafter apply a first voltage, higher than a ground voltage, to the floating common source line.