Semiconductor Device Wiring with Composite Conductive Layers
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Solution Overview
Problem
Semiconductor devices with thin film transistors using oxide semiconductors face challenges in achieving high aperture ratios and low power consumption due to high wiring resistance from light-transmitting conductive materials, which distorts signal waveforms and limits display performance, especially in large display devices.
Innovation Solution
A semiconductor device design that incorporates a gate wiring and source wiring formed by stacking light-transmitting and light-blocking conductive layers, reducing wiring resistance and power consumption, while allowing light transmission through transistor and capacitor regions to enhance aperture ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If light-transmitting conductive material is used for gate and source wirings, then aperture ratio is improved, but wiring resistance increases
Solution Approach 1:
The patent applies composite materials by stacking a light-transmitting conductive layer (such as ITO or IZO) and a light-blocking conductive layer (such as Al or Mo) to form gate and source wirings. This composite structure allows the light-transmitting layer to maintain high aperture ratio while the light-blocking layer provides low wiring resistance, thereby resolving the contradiction between aperture ratio and wiring resistance.
2Reliability
If light-blocking conductive material is used for gate and source wirings, then wiring resistance is reduced, but aperture ratio decreases
Solution Approach 1:
The patent uses a composite structure where a light-transmitting conductive layer is stacked with a light-blocking conductive layer. The light-transmitting layer is positioned to face the light-emitting element, allowing light to pass through and maintain high aperture ratio, while the light-blocking layer provides the necessary low wiring resistance for reliable signal transmission.
3Area of stationary object
If wiring length is increased in large display devices, then display area is expanded, but voltage drop increases
Solution Approach 1:
The patent applies composite conductive layers in gate and source wirings to reduce wiring resistance. By stacking light-transmitting and light-blocking conductive layers, the overall wiring resistance is reduced, which minimizes voltage drop and power loss in large display devices with extended wiring lengths, thereby enabling expanded display areas without excessive energy loss.
Data Source
AI summary
A semiconductor device includes an oxide semiconductor layer provided over a substrate having an insulating surface; a gate insulating film covering the oxide semiconductor layer; a first conductive layer and a second conductive layer laminated in this order over the gate insulating film; an insulating film covering the oxide semiconductor layer and a gate wiring including a gate electrode (the first and second conductive layers); and a third conductive layer and a fourth conductive layer laminated in this order over the insulating film and electrically connected to the oxide semiconductor layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. A source electrode is formed using the third conductive layer. A source wiring is formed using the third conductive layer and the fourth conductive layer.