Semiconductor Device With Concentric Gate Rings
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Solution Overview
Problem
Existing analog/RF semiconductor devices face a trade-off between on-current, parasitic capacitance, and on-resistance, where optimizing one characteristic often adversely affects the others, hindering overall performance.
Innovation Solution
A semiconductor device with concentrically arranged gate rings, equipotentially interconnected by connecting structures, and electrically floating second doping regions, which allows for higher on-current, lower parasitic capacitance, and lower on-resistance through multi-directional and parallel-connected current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If parallel-connected gates are formed to boost on-current, then on-current is improved, but parasitic capacitance is adversely increased
Solution Approach 1:
The gate is segmented into multiple gate rings (first gate ring, second gate ring, third gate ring) that are spatially separated by second doping regions. This segmentation allows each gate ring to function as an independent gate electrode, enabling parallel current conduction paths while reducing the overlapping area between gate and channel, thereby reducing parasitic capacitance.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stacked gate configuration with gate rings arranged at different vertical levels and radial positions. The gate rings are spaced apart by second doping regions, creating a multi-dimensional architecture that increases effective gate area for current conduction while minimizing parasitic capacitance through spatial separation.
2Object-generated harmful factors
If serially-connected gates are formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but on-resistance is adversely increased
Solution Approach 1:
Multiple gate rings are electrically connected in parallel through conducting structures that connect corresponding regions of adjacent gate rings. This merging of gate rings in parallel configuration reduces on-resistance by providing multiple parallel current conduction paths, while the spatial separation by second doping regions maintains low parasitic capacitance.
3Power
If multiple gate rings are interconnected to improve on-current, then on-current is improved, but device complexity is adversely increased
Solution Approach 1:
The second doping regions serve multiple functions: they act as electrical isolators between adjacent gate rings, provide mechanical spacing to define gate ring positions, and function as part of the overall device structure for stress control. This multi-functionality reduces the need for additional separate components, thereby reducing device complexity despite the multi-ring configuration.
Solution Approach 2:
Corresponding regions of adjacent gate rings are electrically connected through conducting structures to maintain equipotential conditions. This ensures uniform voltage distribution across all gate rings, simplifying the electrical behavior and making the device easier to control and model, thereby reducing operational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved performance by enabling larger on-current and lower on-resistance while reducing parasitic capacitance, with an asymmetric source/drain structure and serial-connected stacked gate channels, optimizing electrical characteristics for better analog/RF performance.
Implementation Method 1
a second doping region formed in the substrate and interposed between each two adjacent gate rings... the second doping region is electrically floating
Implementation Method 2
All of the gate rings are equipotentially interconnected by a connecting structure
Implementation Method 3
The first doping region, the third doping region and the gate rings are electrically connected to respective external bias voltages... enabling larger on-current and lower on-resistance with multi-directional and parallel-connected current paths
Data Source
AI summary
A semiconductor device is disclosed, including a plurality of gate rings formed on a substrate and concentrically surrounding a first doped region formed in the substrate. The gate rings are equipotentially interconnected by at least a connecting structure. A second doped region is formed in the substrate, exposed from the space between adjacent gate rings. A third doped region is formed in the substrate adjacent to the outer perimeter of the outermost gate ring. The first doped region, the third doped region and the gate rings are electrically biased and the second doped regions are electrically floating.