Semiconductor Circuit Conductive Bonding Region for Vertical Integration
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming both horizontal and vertical semiconductor devices on a single substrate due to incompatible masks and heat-related damage from laser crystallization methods, which complicates processing and increases area occupancy for memory circuits like SRAM.
Innovation Solution
A semiconductor circuit structure is developed with a conductive bonding region comprising a conductive layer, barrier layer, and bonding layer, which facilitates the formation of vertically oriented semiconductor devices with improved conductivity and bonding strength, reducing signal attenuation and noise, and allowing for the integration of both horizontal and vertical devices on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser crystallization is used to form vertically oriented semiconductor devices, then single crystalline semiconductor material is achieved, but heat flows to proximate regions causing damage
Solution Approach 1:
A conductive bonding region with multiple layers (conductive layer, barrier layer, bonding layer) is introduced as an intermediary between the vertically oriented semiconductor device and the substrate. This bonding region acts as a heat sink and thermal management structure, absorbing excess heat from laser crystallization and preventing it from damaging proximate regions while maintaining the single crystalline quality of the semiconductor material.
Solution Approach 2:
The patent modifies the substrate structure by adding a conductive bonding region with specific electrical and thermal conductivity parameters. The conductive layer, barrier layer, and bonding layer are designed with specific thicknesses and material properties to optimize heat dissipation and electrical connectivity, thereby controlling the thermal parameters during laser crystallization to prevent damage.
2Area of stationary object
If both horizontal and vertical semiconductor devices are formed on a single substrate, then area occupancy is reduced, but mask compatibility becomes incompatible
Solution Approach 1:
The patent transitions from forming all devices in a single planar layer to creating vertically oriented semiconductor devices that extend perpendicular to the substrate surface. This dimensional change allows horizontal and vertical devices to coexist on the same substrate without requiring the same mask patterns, as the vertical devices are formed through different processing steps that are not constrained by the mask compatibility issues affecting horizontal devices.
3Reliability
If SRAM memory circuit includes six transistors per unit cell, then memory functionality is improved, but area occupancy increases
Solution Approach 1:
The patent employs vertically oriented transistors that extend perpendicular to the substrate surface, allowing the six-transistor SRAM unit cell to be formed in a three-dimensional configuration. This vertical integration reduces the lateral footprint of each transistor and the overall unit cell area while maintaining the necessary transistor count and memory functionality, effectively decoupling device complexity from area occupancy.
Data Source
AI summary
A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.