Semiconductor Structure with 3D Printed Conductive Bumps
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Solution Overview
Problem
Conventional wire-bonding techniques in semiconductor manufacturing often result in short circuits and open circuits due to wire movement, and require specific tools and platforms for different products, leading to increased costs and complexity.
Innovation Solution
The use of 3-D printing to form conductive bumps on chips and substrates, connected via a flexible printed circuit (FPC) board, eliminating the need for wire-bonding and allowing for flexible electrical connections without the risks of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding technique is used to connect substrate and chip, then electrical connection is achieved, but short circuits and open circuits occur due to wire movement
Solution Approach 1:
The patent replaces the mechanical wire-bonding system with a direct bonding system where conductive bumps are formed on the chip and bonded directly to corresponding contacts on the substrate, eliminating the need for flexible metal wires that can move and cause short circuits or open circuits
Solution Approach 2:
The patent extracts and removes the wire-bonding components (metal wires, wire-bonding device, wire clamper) from the system, replacing them with a direct bump bonding approach that eliminates the harmful effects of wire movement while maintaining electrical connection functionality
2Adaptability or versatility
If specific wire-bonding tools and platforms are prepared for different products, then product-specific connection requirements are met, but cost and device complexity increase
Solution Approach 1:
The patent creates a universal bump bonding process that can be applied to different semiconductor products without requiring product-specific wire-bonding tools or platforms, as the direct bump bonding approach can accommodate various contact and pad configurations through a single manufacturing system
Solution Approach 2:
The patent uses photolithography and printing techniques to create conductive bump patterns on the chip that can be replicated and adapted for different product configurations, eliminating the need for custom wire-bonding setups for each product type
3Productivity
If wire-bonding process is used, then electrical connection is established, but time consumption increases due to tool changes and platform installation
Solution Approach 1:
The patent forms conductive bumps on the chip surface in advance during the chip fabrication process, so that when the chip is packaged, the bumps are already ready for bonding to the substrate contacts, eliminating the need for time-consuming wire-bonding operations and tool changes during the packaging process
Data Source
AI summary
A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.