Semiconductor Conductive Structure Grain Growth via Thermal Stress
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable semiconductor device structures with increasingly smaller feature sizes, as the scaling-down process complicates fabrication and increases complexity, making it difficult to achieve reliable conductive structures with reduced grain boundaries and lower resistance.
Innovation Solution
A method involving the formation of a stress layer with a different coefficient of thermal expansion than the conductive layer, applied during an annealing process to combine crystal grains into larger grains with fewer boundaries, resulting in a conductive structure with reduced resistance and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication complexity increases and manufacturing reliability deteriorates
Solution Approach 1:
The patent applies parameter changes by controlling the coefficient of thermal expansion mismatch between the stress layer and conductive layer, and by adjusting annealing temperature and time parameters to achieve grain growth while maintaining small feature sizes. This resolves the contradiction by enabling reliable fabrication of small-featured structures through optimized thermal processing parameters.
Solution Approach 2:
The patent utilizes thermal expansion differences between materials with different coefficients of thermal expansion. The stress layer is specifically selected to have a different CTE than the conductive layer, creating thermal stress during annealing that drives grain boundary migration and grain growth. This enables improved reliability through grain coarsening while maintaining scaled-down feature sizes.
2Quantity of substance
If feature size is decreased to increase functional density, then more devices fit per chip area, but the complexity of fabrication processes increases
Solution Approach 1:
The patent employs thermal expansion mismatch as a self-organizing mechanism during annealing. The differential CTE between stress and conductive layers automatically generates the necessary stress fields to drive grain growth without requiring complex external stress application equipment or multi-step processing, thereby simplifying fabrication while enabling high-density device formation.
Solution Approach 2:
The structure utilizes its own thermal properties to achieve grain growth. The inherent CTE difference between layers causes thermal stress during temperature cycling, which self-generates the driving force for grain boundary migration. This eliminates the need for external intervention or complex processing steps to achieve grain coarsening in scaled structures.
3Stability of the object's composition
If conventional annealing is applied to conductive layers, then crystal grains can grow, but grain boundaries remain numerous resulting in high resistance
Solution Approach 1:
The patent uses thermal expansion mismatch to generate controlled thermal stress during annealing. This stress field preferentially drives grain boundary migration in directions that reduce total grain boundary area, promoting the formation of larger grains with fewer boundaries. The result is improved electrical conductivity and reliability while achieving the desired crystal grain structure stability.
Solution Approach 2:
The patent changes the physical and chemical parameters of the conductive layer by introducing a stress layer with different CTE and performing controlled annealing. This transforms the microstructure from fine-grained to coarse-grained, reducing grain boundary density and improving electrical properties. The parameter changes enable reliable conductive structures despite continued scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases the average grain size of crystal grains in the conductive structure, reducing grain boundaries and enhancing the reliability and conductivity of the semiconductor device, while maintaining alignment with the dielectric layer.
Implementation Method 1
annealing the conductive layer and the stress layer
Implementation Method 2
a coefficient of thermal expansion of the stress layer is different from a coefficient of thermal expansion of the conductive layer
Data Source
AI summary
Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a dielectric layer on the semiconductor substrate. The semiconductor device structure also includes at least one conductive structure embedded in the dielectric layer. A plurality of crystal grains are composed of the conductive structure, and a ratio of an average grain size of the crystal grains to a width of the conductive structure ranges from about 0.75 to about 40.