Semiconductor Conductive Interconnection Patterns via Spacer Formation

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Solution Overview

Problem

As semiconductor devices integrate more densely, forming conductive interconnection patterns with smaller widths and intervals becomes challenging due to the complexity and high failure probability of existing double exposure and double patterning processes in photolithography.

Innovation Solution

A method involving a single spacer forming technique to create conductive interconnection patterns with finer widths and spaces, including forming a stopper layer, intermediate pattern material layer, and conductive material layer, followed by etching and deposition processes to achieve symmetrical patterns with smaller dimensions than those possible in standard photolithography.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithography processes (double exposure, double patterning) are used to form fine patterns, then smaller widths and intervals of conductive interconnection patterns can be achieved, but process complexity increases and failure probability increases

Engineering Contradiction:

Improvewidth and interval of conductive interconnection patternsVSAvoidphotolithography process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the pattern formation process into distinct stages: forming mandrels at a first pitch, depositing spacers, selectively removing portions, and forming final conductive patterns at a smaller second pitch. This segmentation allows complex fine patterns to be created through multiple simpler steps rather than attempting to form them in a single photolithography exposure, thereby reducing process complexity while achieving the desired manufacturing precision

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate structures (mandrels and spacers) that serve as mediators in the pattern formation process. These intermediate patterns are formed at larger dimensions using conventional photolithography, then used as templates to define the final fine-pitch conductive patterns. This intermediary approach enables precise control of small features without directly exposing them to photolithography, reducing both complexity and failure risk

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If double exposure or double patterning processes are used, then finer pattern dimensions can be achieved, but the probability of process failure increases

Engineering Contradiction:

Improvepattern line width and intervalVSAvoidprocess success rate

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent employs spacer structures that are formed conformally on mandrels before the final pattern definition. These spacers act as a cushioning layer that protects against variability in the photolithography process, as their dimensions are determined by conformal deposition thickness rather than direct exposure. This beforehand cushioning reduces process variability and failure probability while enabling finer final pattern dimensions

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent changes the controlling parameter for pattern dimensions from photolithography exposure parameters to deposition thickness parameters. By using conformal spacer deposition, the critical dimensions are controlled by film thickness (a more precise and controllable parameter) rather than optical exposure parameters, thereby improving reliability while achieving finer pattern dimensions

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If standard photolithography is used for conductive interconnection patterns, then process simplicity is maintained, but smaller widths and intervals cannot be achieved

Engineering Contradiction:

Improveprocess simplicityVSAvoidconductive pattern width and space

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring by forming mandrels and spacers with significant height-to-width ratios. This dimensional change allows the final pattern dimensions to be controlled by vertical deposition processes rather than horizontal photolithography processes, enabling smaller widths and intervals while maintaining ease of manufacture through vertically-stacked simple processes

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11456252B2Semiconductor device having symmetric conductive interconnection patterns

Publication Date: 2022.09.27 SK HYNIX INC

AI summary

A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.