Semiconductor Package Conductive Layer Segmentation

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Solution Overview

Problem

The existing semiconductor device packaging process faces challenges with the removal of seed layers, which can lead to delamination and increased costs due to discarded packages that fail electrical tests, especially when the bottom patterned conductive layer has limited bonding to the carrier.

Innovation Solution

A semiconductor device package design featuring a carrier with a patterned passivation layer and a first patterned conductive layer, where the conductive layer is partially converted into an insulation medium, allowing for electrical disconnection and improved handling during manufacturing, reducing delamination risks and enabling cost-effective testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the seed layer is removed after the semiconductor device package is formed, then the RDL structure can be tested for electrical functionality, but the entire package must be discarded if it fails the test, increasing manufacturing cost and waste

Engineering Contradiction:
Improveelectrical test capabilityVSAvoidmanufacturing waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The conductive layer is segmented into multiple portions (first portion, second portion, third portion) that are electrically disconnected from each other. This segmentation allows individual portions to be tested and removed independently, enabling failure isolation without discarding the entire package.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The seed layer is extracted and removed at an intermediate stage before the complete package is formed. This allows electrical testing of the RDL structure to be performed on a modular basis, and only the specific failed portions need to be removed rather than the entire expensive package.

Inventive Principle:
Principle #2Taking out (Extraction)

2Loss of substance

If the seed layer is removed after the bottom patterned conductive layer is formed, then manufacturing cost is reduced by saving failed packages, but the bonding between the conductive layer and carrier becomes insufficient, causing delamination and peeling issues

Engineering Contradiction:
Improvemanufacturing wasteVSAvoidbonding strength
Core Design Contradiction:
Loss of substanceVSStrength

Solution Approach 1:

The conductive layer is prepared with multiple disconnected portions in advance, before final package assembly. This preliminary configuration allows the layer to maintain adequate bonding to the carrier during manufacturing while enabling selective removal of failed portions later through the insulation medium interface.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

An insulation medium is introduced as an intermediary between the carrier and the first portion of the conductive layer. This mediator allows electrical testing to be performed while maintaining physical connection and bonding strength, preventing delamination during the testing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If the bottom patterned conductive layer maintains strong bonding to the carrier for handling, then manufacturing handling is improved, but the layer cannot be selectively removed for testing purposes

Engineering Contradiction:
Improvehandling capabilityVSAvoidtestability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

Different portions of the conductive layer have different local qualities: the second and third portions maintain strong bonding to the carrier for handling, while the first portion is electrically disconnected and can be selectively removed through the insulation medium for testing purposes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11031274B2Semiconductor device packages and method for manufacturing the same
Publication Date: 2021.06.08 ADVANCED SEMICON ENG INC
  • US11031274B2 patent drawing
  • US11031274B2 patent drawing
  • US11031274B2 patent drawing

AI summary

A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.