Semiconductor Conductive Layer Step Etching Alignment
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Solution Overview
Problem
The miniaturization of DRAM storage capacitors increases the demand for precise photo-etching technology, leading to misalignment issues that result in higher resistance or breakage of conductive layers, reducing the contact area and transmission efficiency between storage capacitors and capacitor contacts.
Innovation Solution
A step-by-step etching method is employed to form a conductive layer with first, second, and third conductive parts, where protective layers ensure the second conductive parts remain thick, reducing the risk of breakage and maintaining low resistance, and the alignment accuracy of photo-etching technology is improved by adjusting etching parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo-etching technology is used for patterning the conductive layer, then the conductive layer can be formed with specific patterns, but misalignment occurs between the bottom electrode layer and capacitor contact, causing deformation of the conductive layer pattern
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the sidewalls of the conductive layer before the photo-etching patterning process. This protective layer is formed in advance to prevent misalignment damage during subsequent etching operations, ensuring that even if alignment occurs, the conductive layer structure remains intact and connected between the bottom electrode and capacitor contact.
2Reliability
If the conductive layer is made thinner to reduce resistance, then the contact resistance decreases, but the conductive layer becomes more prone to breakage
Solution Approach 1:
The patent applies local quality by creating a non-uniform thickness distribution in the conductive layer through selective protective layer removal. The conductive layer is made thinner in the center region to reduce resistance, while maintaining thicker portions at critical connection points (bottom electrode interface and capacitor contact interface) where mechanical strength is needed. This localized thickness variation simultaneously achieves low resistance and high strength.
3Area of stationary object
If the storage capacitor area is miniaturized, then the storage capacity density increases, but the photo-etching alignment accuracy requirement becomes more stringent
Solution Approach 1:
The patent applies beforehand cushioning by introducing a protective layer that acts as a buffer against alignment errors. This protective layer provides a margin of error during photo-etching operations, cushioning the system against the increased precision demands caused by miniaturization. Even when alignment deviations occur due to small feature sizes, the protective layer ensures the conductive layer remains connected, preventing complete failure.
Data Source
AI summary
The present disclosure provides a semiconductor device and its preparation method, wherein the preparation method includes providing a substrate, forming bit line units, capacitor contacts and a conductive layer on the substrate, patterning the conductive layer on the substrate by step-by-step etching, etching first grooves to form first conductive parts positioned above the bit line units, protecting sidewalls of the first grooves, and then etching second grooves to form second conductive parts covering sidewalls of the bit line units and third conductive parts covering the capacitor contacts.