Semiconductor Package Conductive Layer Width Optimization
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Solution Overview
Problem
Semiconductor device packages face challenges in achieving a balance between compactness, high reliability, and low conduction loss, with Fan-out packaging being thinner but experiencing higher DC conduction loss due to fine lines with narrow widths, leading to signal distortion and reliability issues.
Innovation Solution
A semiconductor device package design featuring a dielectric layer with a conductive layer having varying widths, where a narrower portion connects to a wider portion to reduce conduction loss while maintaining high-density connections, and grounding structures are integrated to enhance electromagnetic interference protection and signal reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If Fan-out packaging is used to achieve thin profile and high density fine-pitch connection, then package thickness is reduced and I/O pin density is increased, but DC conduction loss increases due to narrow line width
Solution Approach 1:
The conductive layer is designed with non-uniform width, featuring a first portion with greater width and a second portion with lesser width. This local variation in geometry optimizes the balance between conduction loss and signal integrity, allowing the structure to achieve low conduction loss while maintaining compact dimensions.
Solution Approach 2:
The invention changes the geometric parameters of the conductive layer by varying its width along its length. The first portion has a width in the range of about 5 μm to about 15 μm, while the second portion has a width in the range of about 2 μm to about 8 μm. This parameter optimization reduces DC insertion loss while maintaining the thin profile characteristic of Fan-out packaging.
2Quantity of substance
If Fan-out packaging with fine lines is used to accommodate more I/O pins, then connection density is increased, but signal distortion occurs due to higher insertion loss
Solution Approach 1:
The conductive layer transitions from a first portion with greater width to a second portion with lesser width, creating optimal local impedance characteristics. This local quality variation maintains signal integrity by controlling impedance transitions while enabling high-density I/O connections through the narrower second portion.
Solution Approach 2:
The invention utilizes the vertical dimension by stacking multiple conductive layers at different heights within the package structure. This multi-layer approach allows high I/O pin density to be achieved without compromising signal integrity, as each layer can be optimized independently for its specific function.
3Loss of energy
If FCBGA structure is used to achieve lower conduction loss, then DC conduction loss is reduced, but package thickness increases and line/space width increases
Solution Approach 1:
The invention optimizes the width parameters of the conductive layer to achieve low conduction loss in a thin package. The first portion width is controlled at about 5 μm to about 15 μm and the second portion width at about 2 μm to about 8 μm, enabling efficient current flow without requiring the greater thickness characteristic of FCBGA structures.
Solution Approach 2:
Instead of increasing thickness to reduce conduction loss as in FCBGA, the invention uses multiple conductive layers stacked in the vertical dimension. This multi-layer configuration provides redundant conduction paths that reduce overall conduction loss while maintaining a thin single-layer footprint.
Data Source
AI summary
A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.